A hardware-centric approach to checking HLS code before synthesis

A hardware-centric approach to checking HLS code before synthesis

September 29, 2021
Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Read the entire article on TechDesignForum originally published...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Speeding Up AI With Vector Instructions

SemiEngineering: Speeding Up AI With Vector Instructions

November 4, 2020
Excerpt from article: “Speeding Up AI With Vector Instructions” SoC designers get these benefits for free, as it is contained...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Week In Review: Design, Low Power

SemiEngineering: Week In Review: Design, Low Power

October 23, 2020
Excerpt from article: “Week In Review: Design, Low Power“ Arm and Mentor are teaming up on a RTL Verification Design...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Custom Designs, Custom Problems

SemiEngineering: Custom Designs, Custom Problems

September 16, 2020
Excerpt from article: “Custom Designs, Custom Problems“ You have to put margin in your architecture. You have to leave a...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: The Evolution Of High-Level Synthesis

SemiEngineering: The Evolution Of High-Level Synthesis

August 27, 2020
Excerpt from article: “The Evolution Of High-Level Synthesis“ The first panelist was Brian Bowyer, director of engineering for Siemens EDA. Bowyer...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Power And Performance Optimization At 7/5/3nm

SemiEngineering: Power And Performance Optimization At 7/5/3nm

August 13, 2020
Excerpt from article: “Power And Performance Optimization At 7/5/3nm“ At the edge, where people are building these new AI processors,...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: #57DAC – Panel Discussion of High Level Synthesis

SemiWiki: #57DAC – Panel Discussion of High Level Synthesis

July 28, 2020
Excerpt from article: “Panel Discussion of High Level Synthesis“ Bryan Bowyer from Siemens EDA was the first to present, and...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: High-Level Synthesis and Open Source Software Algorithms

SemiWiki: High-Level Synthesis and Open Source Software Algorithms

July 14, 2020
Excerpt from article: “High-Level Synthesis and Open Source Software Algorithms“ CircuitSutra is in the process of defining a robust methodology...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Easier Low Power ICs With Reference Flows

SemiEngineering: Easier Low Power ICs With Reference Flows

July 9, 2020
Excerpt from article: “Easier Low Power ICs With Reference Flows” Power-sensitive ICs for wearables and internet of things (IoT) products...
By nileshthiagarajan
< 1 MIN READ
Designing For Extreme Low Power

Designing For Extreme Low Power

July 9, 2020
Excerpt from article: “Designing For Extreme Low Power” There are several techniques available for low power design, but whenever a...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: Why Go Custom in AI Accelerators, Revisited

SemiWiki: Why Go Custom in AI Accelerators, Revisited

June 24, 2020
Excerpt from article: “Why Go Custom in AI Accelerators, Revisited” I believe I asked this question a year or two...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: ML Opening New Doors For FPGAs

SemiEngineering: ML Opening New Doors For FPGAs

June 24, 2020
Excerpt from article: “ML Opening New Doors For FPGAs” FPGAs have long been used in the early stages of any...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: What a Difference an Architecture Makes: Optimizing AI for IoT

SemiWiki: What a Difference an Architecture Makes: Optimizing AI for IoT

May 28, 2020
Excerpt from article: “What a Difference an Architecture Makes: Optimizing AI for IoT” Last week Siemens EDA hosted a virtual...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Inference Moves To The Network

SemiEngineering: Inference Moves To The Network

May 7, 2020
Excerpt from article: “Inference Moves To The Network” Interviews with different players reveal three distinct categories of inference between the...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: The Murky World Of AI Benchmarks

SemiEngineering: The Murky World Of AI Benchmarks

April 30, 2020
Excerpt from article: “The Murky World Of AI Benchmarks” AI startup companies have been emerging at breakneck speed for the...
By nileshthiagarajan
< 1 MIN READ
Designing Ultra Low Power AI Processors

Designing Ultra Low Power AI Processors

April 9, 2020
Excerpt from article: “Designing Ultra Low Power AI Processors” “What makes power such a challenge to get right in an...
By nileshthiagarajan
< 1 MIN READ
New Ways To Optimize Machine Learning

New Ways To Optimize Machine Learning

April 2, 2020
Excerpt from article: “New Ways To Optimize Machine Learning” Some projects are experimenting with larger strides. A stride of 2 means...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: Mentor Masterclass on ML SoC Design

SemiWiki: Mentor Masterclass on ML SoC Design

March 24, 2020
Excerpt from article: “Mentor Masterclass on ML SoC Design” I was scheduled to attend the Siemens EDA tutorial at DVCon...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: High-Level Synthesis at the Edge

SemiWiki: High-Level Synthesis at the Edge

February 19, 2020
Excerpt from article: “High-Level Synthesis at the Edge” Custom AI acceleration continues to gather steam. In the cloud, Alibaba has...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Reducing Power At RTL

SemiEngineering: Reducing Power At RTL

February 13, 2020
Excerpt from article: “Reducing Power At RTL” Other issues Integration is also a consideration. “Accuracy of the power efficiency analysis...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Divided On System Partitioning

SemiEngineering: Divided On System Partitioning

January 30, 2020
Excerpt from article: “Divided On System Partitioning” Building an optimal implementation of a system using a functional description has been...
By nileshthiagarajan
< 1 MIN READ
Priorities Shift In IC Design

Priorities Shift In IC Design

January 16, 2020
Excerpt from article: “Priorities Shift In IC Design” The rush to the edge and new applications around AI are causing...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Improving Algorithms With High-Level Synthesis

SemiEngineering: Improving Algorithms With High-Level Synthesis

December 30, 2019
Excerpt from article: “Improving Algorithms With High-Level Synthesis” Most computer algorithms today are developed in high-level languages on general-purpose computers....
By nileshthiagarajan
< 1 MIN READ
Master the design and verification of next gen transport: Part Two – high-level synthesis

Master the design and verification of next gen transport: Part Two – high-level synthesis

October 2, 2019
Excerpt from article: “Master the design and verification of next gen transport: Part Two – high-level synthesis” Part one of...
By nileshthiagarajan
< 1 MIN READ
AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

September 30, 2019
Excerpt from article: “AI Hardware Summit, Report#2: Lowering Power at the Edge with HLS” I previously wrote a blog about a...
By nileshthiagarajan
< 1 MIN READ
Master the design and verification of next gen transport: Part One – overview

Master the design and verification of next gen transport: Part One – overview

September 30, 2019
Excerpt from article: “Master the design and verification of next gen transport: Part One – overview” The role of high-level...
By nileshthiagarajan
< 1 MIN READ
DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!

DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!

September 19, 2019
Excerpt from article: “DeepChip: Badru wants PnR users to know Nitro-SoC is alive and well and #3!“ John, John, John…...
By nileshthiagarajan
< 1 MIN READ
FPGA Design Tradeoffs Getting Tougher

FPGA Design Tradeoffs Getting Tougher

September 16, 2019
Excerpt from article: “FPGA Design Tradeoffs Getting Tougher” FPGAs are getting larger, more complex, and significantly harder to verify and...
By nileshthiagarajan
< 1 MIN READ
DeepChip: Joe Sawicki on ML, Calibre, Solido, VC funding, and heuristics

DeepChip: Joe Sawicki on ML, Calibre, Solido, VC funding, and heuristics

September 12, 2019
Excerpt from article: “DeepChip: Joe Sawicki on ML, Calibre, Solido, VC funding, and heuristics” Cooley: I mean, what, are you...
By nileshthiagarajan
< 1 MIN READ
EE Journal: Neural Network Notions and Tools

EE Journal: Neural Network Notions and Tools

September 9, 2019
Excerpt from article: “Neural Network Notions and Tools” Tools and Blocks So <deep breath> with all of that under our...
By nileshthiagarajan
< 1 MIN READ
Synthesizing Hardware From Software

Synthesizing Hardware From Software

August 22, 2019
Excerpt from article: “Synthesizing Hardware From Software” In the past, many co-processor solutions have been dogged by communications costs. “There...
By nileshthiagarajan
< 1 MIN READ
Determining Where Power Analysis Matters Most

Determining Where Power Analysis Matters Most

August 8, 2019
Excerpt from article: “Determining Where Power Analysis Matters Most” Getting more granular with power Krishnaswamy noted that RTL power vs. gate...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: Mentor(Siemens EDA) Highlights HLS Customer Use in Automotive Applications

SemiWiki: Mentor(Siemens EDA) Highlights HLS Customer Use in Automotive Applications

July 30, 2019
Excerpt from article: “Mentor Highlights HLS Customer Use in Automotive Applications” This is where HLS shines. You can develop code...
By nileshthiagarajan
< 1 MIN READ
Hardware-Software Co-Design Reappears

Hardware-Software Co-Design Reappears

July 25, 2019
Excerpt from article: “Hardware-Software Co-Design Reappears” It was hoped that co-design would bring hardware and software teams closer together. “It...
By nileshthiagarajan
< 1 MIN READ
Power Is Limiting Machine Learning Deployments

Power Is Limiting Machine Learning Deployments

July 16, 2019
Excerpt from article: “Power Is Limiting Machine Learning Deployments” The total amount of power consumed for machine learning tasks is...
By nileshthiagarajan
< 1 MIN READ
Konica Minolta Talks About High-Level Synthesis using C++

Konica Minolta Talks About High-Level Synthesis using C++

July 11, 2019
Excerpt from article: “Konica Minolta Talks About High-Level Synthesis using C++“ In the early days of chip design circa 1970’s...
By nileshthiagarajan
< 1 MIN READ
C++ signoff made real

C++ signoff made real

July 11, 2019
Excerpt from article: “C++ signoff made real“ Some companies began using high-level synthesis (HLS) for design well before its benefits...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Edge Complexity To Grow For 5G

SemiEngineering: Edge Complexity To Grow For 5G

July 2, 2019
Excerpt from article: “Edge Complexity To Grow For 5G“ Edge computing is becoming as critical to the success of 5G...
By nileshthiagarajan
< 1 MIN READ
Building an ecosystem around HLS for AI and ML designs

Building an ecosystem around HLS for AI and ML designs

June 27, 2019
Excerpt from article: “Building an ecosystem around HLS for AI and ML designs“ HLS has been gaining traction in AI because,...
By nileshthiagarajan
< 1 MIN READ
Providing An AI Accelerator Ecosystem

Providing An AI Accelerator Ecosystem

June 27, 2019
Excerpt from article: “Providing An AI Accelerator Ecosystem“ A key design area for AI systems is the creation of Machine...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: Why Go Custom in AI Accelerators, Revisited

SemiWiki: Why Go Custom in AI Accelerators, Revisited

June 24, 2019
Excerpt from article: “Why Go Custom in AI Accelerators, Revisited“ I believe I asked this question a year or two...
By nileshthiagarajan
< 1 MIN READ
Machine Learning Drives High-Level Synthesis Boom

Machine Learning Drives High-Level Synthesis Boom

June 6, 2019
Excerpt from article: “Machine Learning Drives High-Level Synthesis Boom“ High-level synthesis (HLS) is experiencing a new wave of popularity, driven...
By nileshthiagarajan
< 1 MIN READ
EE DesignIt: Delivering Smarter Faster With Toolkit for IC Innovation

EE DesignIt: Delivering Smarter Faster With Toolkit for IC Innovation

May 28, 2019
Excerpt from article: “Delivering Smarter Faster With Toolkit for IC Innovation“ The new Catapult software High-Level Synthesis (HLS) AI Toolkit...
By nileshthiagarajan
< 1 MIN READ
Mentor Extends AI Footprint

Mentor Extends AI Footprint

May 23, 2019
Excerpt from article: “Mentor Extends AI Footprint“ Siemens EDA are stepping up their game in AI/ML. They already had a...
By nileshthiagarajan
< 1 MIN READ
AI and ML fuel Catapult and Calibre updates

AI and ML fuel Catapult and Calibre updates

May 23, 2019
Excerpt from article: “AI and ML fuel Catapult and Calibre updates“ Catapult HLS AI As more processing necessarily moves away...
By nileshthiagarajan
< 1 MIN READ
Mentor Juices AI Chips with AI

Mentor Juices AI Chips with AI

May 23, 2019
Excerpt from article: “Mentor Juices AI Chips with AI“ On the brink of the Design Automation Conference (DAC), EDA companies...
By nileshthiagarajan
< 1 MIN READ
SemiEngineering: Raising The Abstraction Level For Power

SemiEngineering: Raising The Abstraction Level For Power

May 9, 2019
Excerpt from article: “Raising the Abstraction Level for Power“ Architectural Power Early analysis can lead to the largest gains. “Certainly, higher...
By nileshthiagarajan
< 1 MIN READ
EE Journal: Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP

EE Journal: Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP

April 2, 2019
Excerpt from article: “Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP“ Siemens EDA‘s Catapult™ HLS design tools...
By nileshthiagarajan
< 1 MIN READ
High-level synthesis for AI: Part One

High-level synthesis for AI: Part One

March 26, 2019
Excerpt from article: “High-level synthesis for AI: Part One“ HLS shortens design cycles by raising design abstraction above RTL, typically...
By nileshthiagarajan
< 1 MIN READ
Using Less Power At The Same Node

Using Less Power At The Same Node

March 14, 2019
Excerpt from article: “Using Less Power At The Same Node“ “GPUs and artificial intelligence do require the new nodes, but it is...
By nileshthiagarajan
< 1 MIN READ
SemiWiki: Mentor Showcases Digital Twin Demo

SemiWiki: Mentor Showcases Digital Twin Demo

March 6, 2019
Excerpt from article: “Mentor Showcases Digital Twin Demo“ Siemens EDA put on a very interesting tutorial at DVCon this year. Commonly...
By nileshthiagarajan
< 1 MIN READ
Tech Design Forum: Catapult HLS Integrates eFPGA IP for Faster Development

Tech Design Forum: Catapult HLS Integrates eFPGA IP for Faster Development

March 2, 2019
Excerpt from article: “Catapult HLS Integrates eFPGA IP for Faster Development“ Siemens EDA is looking to extend the configurability options...
By nileshthiagarajan
< 1 MIN READ