PCB traces and impedance planning

Minimizing insertion loss: Why understanding trace width is critical at high frequencies

Material matters An engineer asked me recently about the relationship between trace width and insertion loss while adjusting dielectric height…

ECAD/MCAD collaboration is no longer optional — it’s survival 

In this episode of the Printed Circuit Podcast, host Steph Chavez welcomes two long-time friends and PCB design veterans —…

fabricator etching a PCB

Etch effects exposed: discover where your copper really goes

Etching inner layers involves cleaning the copper on both sides of the piece of laminate, applying a photoresist, exposing the photoresist to create the inner layer pattern, developing the resist, etching away the unwanted copper, and removing the etch resist. This process is automated in most shops and the chemistry is automatically monitored. As a result, the accuracy and repeatability is quite good. It is possible to etch inner layer traces using this process to an accuracy of ±0.5 mils. This accuracy control helps keep impedance within the tolerances required for transmission lines.

Graphic output of surface methodology from HyperLynx DSE

Accelerating the search through millions of “what if” scenarios

HyperLynx Design Space Exploration can help you optimize your design’s performance by exploring a very large design space in a fraction of the time required with traditional methods.

Design smarter, not harder: Evolving design reuse methodologies in EDA

In this episode of the Printed Circuit Podcast, host Steph Chavez explores the growing impact of design reuse in electronic design automation (EDA),…

Fragmented pillars representing fragmented data.

From fragmented to connected: Rethinking the electronics design journey

How digital design threads connect concept, design, and manufacturing to reduce risk, rework, and time to market.

An engineer using PartQuest Design Enablement software

Why the engineer’s design journey is becoming the new competitive battleground

Many hardware engineers today navigate an increasingly fragmented digital landscape. The white paper discusses design enablement as a modern solution — one that transforms component manufacturers from passive content providers into active design partners.

dielectric material loss

Cutting your losses – loss planning and you

Loss planning – What is the best laminate for a loss budget of x dB for y inches?  I was thinking in terms of Panasonic Megaton (sic) 6 or something like it.

A board design from AMD seen in Siemens software

Verification and optimization of power delivery networks for AMD Versal devices

While ensuring stable power delivery is paramount, overengineering power delivery networks (PDNs) can negatively impact product costs and time-to-market.