You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation. IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface. These models are an addendum to the existing IBIS spec that contain executable models.
Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model. The executable model is really the “meat” of the model, but the analog model and parameter file are just as important. The analog model is written like a traditional IBIS model, and is necessary to get the impulse response of the channel to send into the executable part of the model. The parameter file is what allows the simulation program, like HyperLynx, to interface with the executable model. IBIS-AMI models actually work kind of like a FastEye simulation, in that they rely on a pulse response to characterize the channel.
IBIS-AMI marks another step in support of SERDES models by the IBIS committee. Several years ago they also ratified multi-language modeling extensions that allowed IBIS models to map to models of different modeling languages, like SPICE and VHDL-AMS. Mentor continues to work with the IBIS committee to develop and improve this specification so that it may be used to simulate many different types of SERDES buffers.
To find out more, take a peek at my recent article in PCD&F at: