How to run your SSN datapath at double your I/O data rate 

Imagine your chip’s internal SSN bus is a super-fast highway, capable of handling data at 400 MHz. However, the external connections, like your standard GPIO pads, might only be able to manage 200 MHz. If you simply connect them directly, your internal highway is forced to slow down, resulting in a lower bandwidth. 

The Solution: BusFrequencyMultiplier and BusFrequencyDivider to the Rescue!

This allows speeding up the data rate on the narrower internal bus while still allowing the wider I/O bus to operate at half the data rate. 

You can route a 400 MHz 32-bit bus inside the chip while using a 200 MHz 64-bit bus to interact with the tester. This keeps the internal bus speed higher with a narrower bus which is easier to route between the physical blocks. 

How it Works:

1. Input Side: The BusFrequencyMultiplier (BFM) 

• On the input side, you’ll use a BusFrequencyMultiplier (BFM) node. Think of the BFM as an accelerator. 

• It takes the incoming data, which is running at the slower external data rate (e.g., 200 MHz) and speeds up the data rate on the internal bus by a factor of 2 while making the output bus half as wide.  

• While the external pads are still providing data at 200 MHz, the BFM samples this data at every other clock edge of the SSN bus clock of 400 MHz, effectively doubling the data rate for the internal bus. The BFM’s output then provides data on every edge of the faster internal SSN bus clock. 

2. Output Side: The BusFrequencyDivider (BFD) 

• On the output side, you’ll employ a BusFrequencyDivider (BFD) node. This acts as a decelerator. 

• It takes the faster internal data (e.g., 400 MHz) and halves the output data rate for the I/O while doubling the output bus. 

A quick note on clocking: To achieve this faster internal speed, the SSN datapath requires a dedicated, faster internal clock. The faster clock is supplied from an input pad and is automatically managed by Tessent as “tester x2,” meaning it pulses twice per tester cycle. 

Easing Timing Closure: The OutputPipeline Node

You also use an OutputPipeline node between the BusFrequencyDivider node and the output pads to step down the bus clock distribution tree and avoid having the bus clock distribution tree delay in the loop timing path. The clock input for the OutputPipeline node is local to the physical region containing the output pads and the OutputPipeline node. 

Summary:

By implementing a BFM/BFD pair, you can have a 400 MHz 32-bit bus inside the chip while using a 200 MHz 64-bit bus to interact with the tester. This allows you to run your SSN datapath twice as fast as your I/O data rate. 

For more details including an example SSN datapath along with an accompanying waveform, please refer to the Siemens support knowledge base article: How to use a BFM/BFD pair to enable the SSN datapath to run faster than the IO