Accelerating Digital Design: New Library Generation and Analysis Flows from Google-Siemens EDA Collaboration at DAC

By Emma-Jane Crozier

From rapid library generation to precise analytics, Google and Siemens EDA’s latest collaboration presented at the Design Automation Conference (DAC) tackles some of the biggest challenges in mobile SoC development.

The Liberty challenge in mobile SoC design

For anyone working on mobile SoCs, Liberty (.lib) files are essential for chip implementation and sign-off. But there are big challenges: Process Design Kits (PDKs) change quickly, sometimes just right before tape-out, and there is a need for a lot of different Process, Voltage, and Temperature (PVT) libraries to cover wide voltage ranges. Historically, these complexities have made library decision-making a time-consuming step.

At DAC, Google and Siemens EDA presented some new ways to handle these issues. They showed how to compare important details in Liberty files and how to create these files much faster and more flexibly. This collaboration offers practical solutions to speed up verification and development, overall making designs more reliable. Let’s look at how their methods for comparing, generating, and parsing Liberty data can help improve digital design.

Three innovative approaches presented at DAC

The presentation highlighted flows for comparing critical parameters in liberty files, alongside a methodology for producing liberty files quickly and flexibly.

Liberty comparison flow

This standard cell liberty comparison flow is used to compare all the attributes present in the liberty file with the help of the Solido Analytics tool. Designers can assess critical parameters like speed, variation, input pin capacitance, and power characteristics early in development. This offers advantages over traditional RO SPICE simulations, helping reduce costly late-stage design iterations and accelerating time-to-market.

💡Key takeaway: Early and accurate assessment across PDK and technology changes for impact analysis and informed decision-making.

Library generation flow

In this flow, the AI-powered Solido Generator tool accelerates liberty generation for intermediate and extreme corners. It rapidly generates interpolated temperature corner libraries, validated within 1-2% (3-4% at lower VDD) of characterized data, mitigating schedule impacts. For extreme corners, it extrapolates high-voltage libraries with 2-3% SPICE correlation, delivering crucial schedule savings and enabling faster design iterations.

💡Key takeaway: Reduced overall characterization runtime accomplished with reasonable accuracy.

Library data parser flow

Built on Solido Analytics, this solution advances design analysis. It allows engineers to extract detailed parameter data and implement custom checks, providing insight into cell-specific behavior. The result is a more robust debugging and analysis process that can identify potential issues early in the design cycle, helping engineers pinpoint and resolve problems quickly and precisely.

💡Key takeaway: Analysis to find root causes of outliers alongside understanding general behavior of cells.

Optimizing liberty file workflows: the real-world benefits for mobile SoC design

The collaboration between Google and Siemens EDA showcased at DAC represents a significant advancement in addressing liberty file challenges. By dramatically reducing characterization time, design teams can accelerate their development cycles while maintaining accuracy. The ability to identify PDK and technology impacts early in the design process enables teams to make data-driven decisions, helping prevent costly late-stage revisions. These improvements are particularly valuable for mobile SoC designs where time-to-market pressures and complex multi-corner requirements intersect.

This presentation was developed by: