Improving consistency of NLDM and CCS models for better signoff convergence The semiconductor industry has…

Smart Power Designs: Reality or Buzz?

We are in a generation where “intelligent” devices are pervasive in our daily lives. We…

Improving Time-to-Market and Silicon Quality with a Streamlined IP QA Flow

Recently Felipe Schneider (from the Solido Crosscheck applications engineering team) and I hosted a live…

A Practical Approach to Utilizing the Open Model Interface (OMI) in Aging Analyses for Long Term Reliability Validation

Long term reliability has always been a focus for the automotive industry but is now…

What is the winning formula for running library characterization on the cloud?

According to IDG’s 2020 Cloud Computing Study, 32% of IT budgets in organizations will be…

Thorough variation-aware verification: proving vital for modern power-efficient designs

Recently the Institute of Electrical and Electronics Engineers (IEEE) awarded STMicroelectronics the “IEEE Milestone for Multiple…

Addressing the Post-Layout Simulation Bottleneck for Analog Verification

Analog and mixed-signal designs are pervasive throughout the technology landscape today. The rapid growth in…

Producing and verifying 7/5/3nm IP Liberty models: the building blocks for leading-edge HPC, ML/AI and 5G designs

The first 5nm production chips have already been launched, such as Apple’s A14 Bionic, Qualcomm’s…

Machine Learning Enabled High-Sigma Verification for Memory Design – Innovation to cure ‘Chip Memory Loss’

The Covid-19 pandemic has presented us with many challenges in this past year. Working from…