Note: If you’re interested in knowing more about Solido Design Environment, check out this executive video by Amit Gupta, VP and GM of Custom IC Verification Division at Siemens EDA.
The landscape of semiconductor design is constantly evolving, with engineers and designers continually seeking innovative solutions to meet the ever-increasing demands of their designs faster and more accurate. At Design Automation Conference (DAC) 2023, we unveiled Solido Design Environment (Solido DE) as a comprehensive AI-powered SPICE-level design environment. I invite you to check out our press release featuring notable customer testimonials from leading organizations such as SK Hynix, Ametek and others.
In this blog, we will discuss the disruptive technologies in Solido Design Environment and highlight the key features that make it a standout choice for chip designers. Before we start, I highly recommend delving into this SemiWiki article, which showcases AI capabilities in the design and verification of Custom, Analog Mixed-Signal ICs.
Adaptive AI: enabling orders of magnitude faster, production-accurate verification
Solido’s Adaptive AI technology significantly accelerates the verification process while maintaining production accuracy. This technology utilizes machine learning to adapt and optimize the verification process in real-time, resulting in faster and more accurate results.
This technology enables users to achieve 3, 4, 5, 6 and higher target sigma verification in a fraction of runtime compared to brute force verification using PVTMC Verifier and High-Sigma Verifier tools in Solido Design Environment. For higher sigma targets such as 6 sigma and higher, verification is generally not feasible, without a solution like this.
Additive Learning: powering up to a 100X boost to existing AI techniques
Solido Design Environment pushes its capabilities with Additive Learning technology, which is a breakthrough approach to AI in the EDA industry.
Additive Learning technology boosts existing AI providing additional speedups on incremental verification runs, after an initial verification run is completed.
Assistive AI: providing 5X-10X productivity boosts
Design optimization is a critical aspect of chip design, especially as SoC designs get bigger and more complex. Solido Design Environment’s Assistive AI technology accelerates time-to-market by assisting the user in achieving their power, performance, and area specifications.
Siemens EDA’s Solido Design Environment has transformed the custom IC design process by offering a comprehensive AI-powered design environment for SPICE-level design and verification. It serves as a unified solution for both nominal and variation analysis, trusted by thousands of designers who rely on it to create cutting-edge products in high-performance computing, AI, IoT, automotive, and mobile applications.