Design for Test: Where Did I Put My Keys?
“Now where did I put my keys?” It doesn’t have to be keys. It could be glasses, cell phone, purse, or any kind of item we normally deal with in our lives. Does it mean our memories are bad? Not necessarily.
I deal with bad memories in my work. In fact, I try to figure out the bad ones from the good ones. No, I’m not some sort of medical or mental health clinician. I’m referring to the memories embedded inside the integrated circuits that are abundant in the electronic devices that touch nearly every part of our lives. I work on test products used by IC design and manufacturing companies. It probably could go unsaid that it is important to test these memories for defects after being manufactured.
Memories used to be external components in and of themselves that were connected to other ICs through circuit boards. There are still some memory devices that fit this description, but over the years memories have migrated into the same chips that contain the other logic required for the IC functionality. Survey results I’ve seen show that it is common for the memories in an IC to take up over 50 percent of the total silicon area of the die, and the percentage is likely to keep growing.
Within an IC, the actual physical structures or feature sizes that make up the memory cells are very tiny and dense; more dense than for the other logic. This causes the memories to be more susceptible to minor defects, hence the need for a thorough test plan to check for defects as part of manufacturing test. To make the test challenge more difficult, memories also come in different sizes, configurations, and speeds.
Test Techniques to the Rescue
There are a number of techniques that can be used to test the different memories in an IC. The best approach will be different based on your test requirements. If the memory was an IP core obtained from a memory provider, it probably came with additional test logic included or at least instructions on how best to test that particular memory.
For medium and large memories, the most common test approach is to add memory BIST, or built-in self test logic. The memory BIST tool can read the design and memory models and find the memories automatically and report them. Then the user can choose how to configure the memory tests for the whole IC. Some of the items to evaluate include:
- Which test algorithms to use with which memories?
- Are any custom algorithms needed, if so, what are they?
- How many BIST controllers to use?
- Which memories can share a controller?
- Will BIST controllers be run in serial or parallel?
- What speeds are required for the tests?
- Will diagnosis be done for any failing memories?
- Is built-in self analysis needed for any memories with repair capabilities?
After the tool has taken all the specified input, it creates the entire memory BIST circuitry and inserts it into the design. In addition to this output, the tool also creates synthesis scripts, test patterns for running on automated test equipment, and a simulation testbench for verification of the BIST circuitry working with the design.
So there are some of the keys to effective memory testing so that defective memories don’t ruin your day. Oh yeah, the keys. Here they are. Now I wonder where I parked the car!
If you’d like to learn the details of using MemoryBIST with your designs, you can take our training course Tessent MemoryBIST . It is offered in instructor led format by our industry expert instructors and also in a self-paced on-demand format. The self-paced course is also available in the Tessent on-demand training library that contains all Tessent self-paced courses. Also, you can now earn a digital badge/level 1 certificate by taking our Tessent MemoryBIST Badging Exam. This will enable you to showcase your knowledge of this topic by displaying the badge in your social media and email signature.
Author: Bruce Swanson, Principal Customer Training Engineer, Siemens EDA Learning Services