Webinar Preview: Practical Flows for Continuous Integration

Webinar Preview: Practical Flows for Continuous Integration

But First, The Backstory… I’ll take you back to May 4th 2020 to the last in a series of verification...
Performance Profiling How-To (Make My Testbench Faster)

Performance Profiling How-To (Make My Testbench Faster)

Here’s the situation… You’re DV lead. You and your team are at month 10 of a 12 month development cycle....
Simulation Performance Profiling Like a Pro

Simulation Performance Profiling Like a Pro

New product development is the fun part of working with Siemens. And over the past 9 months I’ve been lucky...
Qrun-ing Optimized Build Flows in Questasim

Qrun-ing Optimized Build Flows in Questasim

Qrun-ing with Questasim For Questasim users, qrun will be a welcome surprise. Admittedly, I’ve never been a huge fan of...
Expediting Simulation Turn-around Time with Incremental Build Flows

Expediting Simulation Turn-around Time with Incremental Build Flows

Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use...
Formal Flows From a Simulation Point-of-View

Formal Flows From a Simulation Point-of-View

At the end of Your First Step Into Formal Property Checking, I said the effort I put into understanding formal...
Formal Level 6: Property-Driven Development

Formal Level 6: Property-Driven Development

I’ve made it to the end of my formal property checking journey. The final lesson learned? Design engineers can write...
Your First Step Into Formal Property Checking

Your First Step Into Formal Property Checking

I’ve been big on unit testing for a little over 10 years. In fact, I regularly say unit testing is...
I’m Excited About Formal Property Checking! My Journey From Skeptic to Believer

I’m Excited About Formal Property Checking! My Journey From Skeptic to Believer

Yup. You read that right. I’m excited about formal property checking. To put it mildly, this is way out of...
SystemVerilog Race Condition Challenge

SystemVerilog Race Condition Challenge

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that the SystemVerilog language gives developers...
Methodology by Example – 6 Approaches to Verification

Methodology by Example – 6 Approaches to Verification

This blog is an exciting next step – exciting for me at least! – that builds on what I proposed...
The Ideal Verification Timeline

The Ideal Verification Timeline

Our discussion around building integrated verification methodologies started with where techniques apply to design by plotting options for verifying low,...
Tools In A Methodology Toolbox

Tools In A Methodology Toolbox

To understand how techniques fit together as part of a comprehensive verification methodology, we’re mapping techniques as a function of...
Verification Methodology Reset

Verification Methodology Reset

Discussion around verification methodologies have been going on for a couple decades. It started back around 2000 with the emergence...
Building Integrated Verification Flows – Round 2

Building Integrated Verification Flows – Round 2

Verification methodology has been a continuous discussion in our industry for a good 20 years now. I’ve dabbled in that...
Questa VRM is the New MS Project

Questa VRM is the New MS Project

I’ve written extensively about agile development from the point of a verification engineer. From the beginning, I’ve been firmly of...
The Beginning Of The End For Coverage

The Beginning Of The End For Coverage

Before we get started here, I’ll assure you it’s not as it sounds. I’m not talking about the end of...
New Job Excitement

New Job Excitement

This is my first Verification Horizons blog since joining the Mentor Product Engineering team in January. I’m excited to be...