How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,…

How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,…

How to Reduce the Complexity of Formal Analysis – Part 3 – Assertion Decomposition

How to Reduce the Complexity of Formal Analysis – Part 3 – Assertion Decomposition

In Part 2 of this series, we showed how reducing the complexity of you assumptions (a/k/a constraints) can really help…

How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

When using formal property checking, users often encounter “inconclusive” results; meaning the combined complexity of the design, assertions, and assumptions…

How to Reduce the Complexity of Formal Analysis – Part 1 – Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take

How to Reduce the Complexity of Formal Analysis – Part 1 – Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take

When using formal property checking, users often encounter “inconclusive” results; which means that the combined complexity of the design, assertions,…

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May 21-24, 2018 in La Jolla,…

OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

You’ve watched all the Verification Academy videos on getting started with formal verification, and even tried some of the examples…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

In formal verification, proving all of your properties is pretty much the main goal of the whole exercise – if…