How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

Nearly 7 years ago security researchers uncovered how to remotely access and control the steering, cruise control, and braking system…

DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All?

To many of us in the EDA world, using the term “digital twin” to describe how customers’ electronically model their…

DAC 2022: Siemens EDA Experts Share Practical Cloud Solutions

Customers have been running Siemens EDA’s tools and flows in the cloud since 2005; and today at any given time…

Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference

Making sure that digital logic enables secure data to safely flow through a system is a critical task for RTL…

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

RISC-V

Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading…

DVCon USA 2022 How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

With eight papers in two separate sessions focused exclusively on formal verification, one could assert (pun intended) that this year’s…

The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many…

58th Design Automation Conference

Build Your Career by Attending the Static & Formal Verification University at DAC 2021

Among the reasons to go to university are the opportunities to open new career paths by learning new technical skills,…