The Survey Says: Verification Planning

The Survey Says: Verification Planning

As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce…

Redefining Verification Performance (Part 2)

Redefining Verification Performance (Part 2)

In my last blog, I gave a few examples of different ways of thinking about getting more work done by…

Redefining Verification Performance (Part 1)

Redefining Verification Performance (Part 1)

What does the word performance mean to you? Speed? Well, obviously speed is an important characteristic. Yet, if the team…

New Verification Academy Advanced OVM (&UVM) Module

New Verification Academy Advanced OVM (&UVM) Module

I’ve always loved the Chinese proverb, “Give a man a fish and you feed him for a day. Teach a…

DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and Post-Silicon Validation at this year’s …

High-Level Design Validation and Test (HLDVT) 2010

High-Level Design Validation and Test (HLDVT) 2010

I’ve had the pleasure of participating in the IEEE International High-Level Design Validation and Test (HLDVT) workshop off and on…

Debugging requires a multifaceted solution

Debugging requires a multifaceted solution

PROLOGUE: Over the weekend, I was thinking about a recent visit I had with an advanced ASIC team manager who…

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA

I’m excited. I’ve had the pleasure of knowing Cliff Cummings for many years, and I was honored a couple of…

Evolution is a tinkerer

Evolution is a tinkerer

I was recently quoted in an EDA DesignLine blog as saying that “it is a myth that ABV is a…