I’ve had the pleasure of participating in the IEEE International High-Level Design Validation and Test (HLDVT) workshop off and on for the past ten years. In fact, of all the workshops and conferences I attend each year, I would probably rank this workshop up there as as one of my favorites. Each year, I look forward to re-connecting with many wonderful thought leaders from both industry and academia who regularly participate.
At this year’s HLDVT, I am honored to have the opportunity to participate on a panel titled “Clock Domain Verification Challenges.” I’d be interested in hearing your views on the subject, particularly emerging challenges around network-on-chip architectures.
In addition to the panel, this year’s HLDVT provides a rich program with five regular sessions, five special sessions, one tutorial, one keynote speech. There are several areas of intense focus. First, there is a session on firmware validation and one on HW-dependent software, to highlight the importance of embedded software. A session and panel are devoted to multi-clock systems and clock domain crossing verification, deployed in a variety of scenarios. One session is devoted to transaction-level modeling and another one deals with high-level arithmetic circuit descriptions to obtain more from circuits. Industry leaders in Electronic System Level (ESL) design will share their perspectives on verification challenges at ESL, and a variety of papers will deal with formal verification advances, constraint solving, coverage, and verification accelerators and emulators.
This year’s HLDVT workshop, which is scheduled for June 11-12, is co-located with 47th Design Automation Conference, June 13-18, 2010 at the Anaheim Convention Center, Anaheim, CA. For more information, visit http://www.hldvt.com/10/.