Accelerating Verification of Computational Storage Designs (NVMe)

Introduction

Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing data movement. However, this innovation also complicates the design and verification processes. Ensuring the proper functioning of computational storage devices within the existing NVMe infrastructure presents significant challenges requiring advanced verification solutions. Consequently, we are excited to announce that Siemens Avery Verification IP R&D team members Prashant Dixit and Ujjwal Negi will present a paper on these critical issues at the Future of Memory and Storage Conference, August 6-8, 2024, at the Santa Clara Convention Center.

Our session will focus onto verification challenges for NVMe designs associated with Computational Storage and Subsystem Local Memory (SLM) command sets, offering new insights into the cutting-edge methods we employ to tackle verification challenges. The key verification aspects we will cover include: 

Validating Computational/SLM Operations and Data Transfers 

Ensuring compliance with NVMe standards requires: 

• Command Set Validation: Verifying correct implementation and functionality of computational and SLM commands. 

• Data Transfer Verification: Ensuring data transfers are accurate and efficient, adhering to NVMe protocols. 

• Subsystem Compliance: Confirming that the subsystem, including computational elements and local memory, operates within NVMe specifications. 

Enhancing Adaptability with UVM Features 

The Universal Verification Methodology (UVM) enhances adaptability for computational storage designs through: 

• Callbacks: Allowing dynamic modification of verification components to adapt to different device-specific programs without altering high-level stimulus. 

• Analysis Components: Facilitating detailed monitoring and analysis of operations for quicker issue identification. 

Comprehensive Compliance Test Suite and Efficient Debug Mechanisms 

A robust compliance test suite is essential. Key elements include: 

• Exhaustive Test Coverage: Ensuring all scenarios, including edge cases, are tested. 

• Efficient Debug Mechanisms: Providing tools and methodologies for quick and effective debugging to maintain development timelines and quality. 

Diversified Access to Commands, Data Structures, and SLM Ranges 

Diverse access methods ensure thorough testing of computational storage designs by: 

• Command Diversity: Testing a variety of commands for broad compliance and functionality. 

• Data Structure Variability: Simulating different data structures to test robustness. 

• SLM Range Access: Testing local memory operations across different ranges and conditions. 

Conclusion 

Verifying computational storage designs within the NVMe framework presents unique challenges requiring innovative solutions. With the help of Siemens Avery Verification IP, engineers can leverage UVM features, access a full range of comprehensive test suites, and employ efficient debug mechanisms; ensuring their designs meet high standards of quality and performance. This thorough validation is crucial for the successful deployment of computational storage technologies, leading to more efficient and powerful data storage solutions. 

About the Presenters:  

Prashant Dixit is developing verification solutions for UCIe-based designs at Siemens EDA. He manages the Storage Verification IPs team, focusing on NVMe and NVMe over Fabrics testing solutions. Prashant holds a Master of Engineering degree in Microelectronics from BITS Pilani, completed in 2006. 

Ujjwal Negi is currently working on the development of verification solutions for NVMe and NVMe over Fabrics testing solutions in storage domain focusing on the Computational Storage. Ujjwal holds a Bachelor of Technology in Electronics and Communication from Guru Govind Singh Indraprastha University in 2023. 

We also welcome you to come to our booth (1051) to meet with our presenters and our other experts at the conference. Hope to see you there!