Part 1: The 2018 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2018 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings from this study will be presented in a set of upcoming blogs. In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity.

The Global FPGA Semiconductor Market

The global semiconductor market was valued at $444.70 billion in 2017, of which, $4.7 billion is accounted for by FPGAs [1][2]. The FPGA market is expected to reach a value of $8.8 billion by 2027, growing at a compounded annual growth rate (CAGR) of 6.4% during this forecast period. The growth in this market is being driven by new and expanding end-user applications related to automotive, IoT, telecommunication, industrial, mil/aero, consumer, and emerging AI applications within the data center requiring acceleration.

Historically, FPGAs have offered two primary advantages over ASICs. First, due to their low NRE [3], FPGAs are generally more cost effective than IC/ASICs for low-volume production. Second, FPGAs’ rapid prototyping capabilities and flexibility can reduce the development schedule since a majority of the verification and validation cycles have traditionally been performed in the lab. More recently, FPGAs offer advantages related to performance for certain accelerated applications by exploiting hardware parallelism (e.g., AI Neural Networks).

The IC/ASIC market in the mid- to late-2000 timeframe underwent growing pains to address increased verification complexity. Similarly, we find today’s FPGA market is being forced to address growing verification complexity. With the increased capacity and capability of today’s complex FPGAs, and the emergence of high-performance SoC programmable FPGAs (e.g., Xilinx Zynq, Altera Arria, Altera Cyclone, Altera Stratix, and Microsemi SmartFusion), traditional lab-based approaches to FPGA verification and validation are becoming less effective. Later in this blog series, we will quantify the ineffectiveness of many of today’s FPGA verification processes in terms of non-trivial bug escapes into production.

FPGA DESIGN TRENDS

One industry driver that has had a substantial impact on FPGA design and verification complexity is the emergence of new layers of design requirements (beyond basic functionality), which did not exist years ago, for example, clocking requirements, security requirements, safety requirements, and requirements associated with hardware-software interactions. In this section, we examine trends related to various aspects of growing FPGA design complexity.

Embedded Processor Cores

What has changed significantly in FPGA designs in the last fifteen years is the movement toward SoC-class designs. For example, our study found that 64% of all projects targeted their design at an FPGA containing one or more embedded processors, as shown in Fig. 1-1. Furthermore, 43% of all FPGA designs today contain two or more embedded processors, while 14% include four or more embedded processors. SoC-class designs add a new layer of verification complexity to the verification process [4] that did not exist with traditional non SoC-class designs due to increased number of design requirements. For example, SoC-class designs often require verification of hardware and software interactions, new coherency architectures, and complex network-on-a-chip interconnect.

 Fig. 1-1. Number of embedded processor cores

Asynchronous Clock Domains

In Fig. 1-2, we see that 90% of designs being implemented as FPGAs contain two or more asynchronous clock domains. Verifying requirements associated with multiple asynchronous clock domains has increased both the verification workload and complexity. For example, a class of metastability bugs cannot be demonstrated on an RTL model using simulation. To simulate these issues requires a gate-level model with timing, which is often not available until later stages in the design flow. However, static clock-domain crossing (CDC) verification tools have emerged and are being adopted to help identify clock domain issues directly on an RTL model at earlier stages in the design flow.

  Fig. 1-2. Number of asynchronous clock domains

Security Features

Recently, we are seeing increases in the number of projects implementing security features in their designs, as shown in Fig. 1-3. Examples of security features include security assurance hardware modules (e.g., a security controller) that are designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords, and biometrics reference data. These security features add requirements and complexity to the verification process.

 Fig. 1-3. FPGA design projects implementing security features

Safety-Critical Design

Another example of increasing requirements contributing to complexity relates to safety-critical designs. In Fig. 1-4, we see an increase in the number of FPGA projects working under one of multiple safety-critical development process standards or guidelines.

 Fig. 1-4. FPGA design projects working on a safety-critical design

For those projects working under a safety-critical development process standard or guideline, in Fig. 1-5 we show the specific breakdown for the various standards. Note that some projects are required to work under multiple safety standards or guidelines. For example, IEC61508 and IEC61511.

Fig. 1-5. Safety-critical development standard used on FPGA project

The key takeaway from this blog is that FPGA designs are growing in complexity, which impacts verification effort and effectiveness.

In my next blog (click here), I’ll focus on verification effectiveness trends related to FPGA designs.

Quick links to the 2018 Wilson Research Group Study results

References

[1]      IC Insights, The Mid-Year Update to the McClain Report, 2018.

[2]      International Business Strategies, Semiconductor Market Analysis, 2017 Review, 2018 Projections, February 14, 2018.

[3]      S. Trimberger, Three ages of FPGAs: a retrospective on the first thrity years of FPGA Technology, Proceedings of the IEEE, Vol 103, Issue 3, March 2015.

[4]      W. Chen, Member, S. Ray, M. Abadir, J. Bhadra, Li-C Wang, Challenges and Trends in Modern SoC Design Verification, IEEE Design & Test,Vol 34, Issue: 5, Oct. 2017.

Comments

0 thoughts on “Part 1: The 2018 Wilson Research Group Functional Verification Study

Leave a Reply