Thought Leadership

Time hogs, blogs, and evolving underdogs…

I realized a few years back that “time” is an engineer’s most precious resource. It seems that there’s just never enough time. And that certainly impacts the way we all consume information. In fact, if you’re like me, my favorite tool for seeking information these days is Google. I usually end up skimming the first few sentences to quickly determine if the information is relevant to me. I like having control of what I consume, and that is why I like blogs.

Hence, I’m excited to have the opportunity to participate in the Verification Horizon Blog. I hope we can create a wonderful experience for exchanging various ideas and thoughts on advanced functional verification in a fashion that allows you to consume relevant information in an efficient manner. I look forward to your participation in our various discussions.

Speaking of consuming relevant information, I would like to encourage you to visit Mentor Graphic’s Verification Academy. We just recently released two sessions for a new module that focuses specifically on FPGA verification. This module is based on Ray Salemi’s book, FPGA Simulation.  In fact, I’m excited to announce that Ray is the subject matter expert (SME) and presenter for these new sessions. Our goal in creating this special module is to provide a step-by-step guide to evolving an FPGA project team’s verification capabilities. Our first session is about code coverage techniques. We are actively working on additional sessions that cover the topics of test planning, FPGA-focused assertions, transactions, self-checking testbenches, automatic stimulus, and functional coverage. Although this particular module targets project teams in the FPGA space, it also provides an excellent basic introduction to advanced functional verification techniques.

And while you are at it, check out our other released modules on Evolving Capabilities, Clock Domain Crossing, and Assertion-Based Verification.  I would love to hear your feedback, suggestions, and directions for new content!

Harry Foster

Harry Foster is Chief Scientist Verification for the Design Verification Technology Division of Mentor, A Siemens Business; and is the Co-Founder and Executive Editor for the Verification Academy. In addition, Harry is serving as the 2021 Design Automation Conference General Chair. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2009/12/04/time-hogs-blogs-and-evolving-underdogs/