The best paper of the 2020 symposium describes a layout-friendly EDT decompressor that reduces routing congestion associated with decompressor circuitry…
Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of glory. This one will be…
By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago
By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.
By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.
By Rick Fisette, Mentor Graphics Is DFT a barrier to tapeout? Time to consider going hierarchical.
By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume
By Ron Press Inserting test compression logic just got a lot easier.
