Video: Seagate presents RISC-V debug and optimization with Tessent

Richard Bohn, the engineering director of advanced IP development at Seagate Technology, shares their strategy for debug and optimization in tomorrow’s storage technology. This video was recorded at the User2User 2023 North America symposium.

Bohn gives an overview of Seagate Technology, discusses some of their challenges, how they have worked with the Tessent group over the years, and describes how they use the Tessent Embedded Analytics products to improve their debug and optimization. The session ends with a Q&A session with the audience of test professionals.

Seagate needed RISC-V debug and high-speed data trace for their high-performance core. They needed to be able to trace for longer time periods, reduce trace memory buffer requirements, avoid trace loss due to backpressure and reduce bandwidth requirements on the off-chip transport system. Siemens has made active and extensive contributions to the development of the RISC-V ecosystem since 2016, and worked with Seagate to develop a trace functionality to meet their needs. The Tessent solution for RISC-V trace provides the most efficient solution for all Seagate’s requirements, allowing an understanding of program behavior even in the most complex multicore systems.

To learn more about Tessent’s RISC-V trace, download the RISC-V Enhanced trace encoder fact sheet.