Learn about how Mentor and our partners, Advantest and Teradyne, are getting behind the IEEE 1149.10 standard for re-use of high-speed IOs/ SERDES for scan test at ITC
At ITC 2019, you can learn more about Mentor’s collaboration with key industry players to bring 1149.10 to life in our ITC booth theater.
- Tuesday, 12 November at 4:35 PM, join JF Cote of Mentor and Michael Braun of Advantest.
- Wednesday, 13 November, at 12:40 PM, JF will be joined by Shawn Sullivan of Teradyne.
Constant increases in design size has always been a challenge for IC test. Test costs have been controlled as design sizes have grown exponentially, largely because of improvements in test compression.
However, the number of pins accessible for scan test, GPIO pins, is not growing because ICs need more and more high-speed pins. A holy grail in IC test is therefore to re-use high speed IOs (called HSIOs or SERDES) for scan test. This is easier said than done because even though a solution needs to work with the existing tester hardware, changes will still be required in the entire ecosystem from DFT to ATE. At the same time it is important to not impact the IO design or functional operation of the chip.
Several industry players, including Mentor, Test Insight, Teradyne, and Advantest, are working towards an end-to-end solution based on IEEE 1149.10 standard for re-using high speed IOs for scan test. IEEE 1149.10, approved in May 2017, defines circuitry for testing ICs through a high-speed TAP with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated.
This particular approach has several advantages, including maintaining testability of the functional path, and being future-proof against future functional high speed protocols.
Come to the Mentor booth #401 at ITC in Washington DC from 12-14 November 2019 to learn more about test solutions based on IEEE 1149.10.
For information about all of Mentor’s activities at ITC 2019, visit our website.