Better Stimulus Generation Through AI: Shaping the Future of Functional Verification
Join host Harry Foster on Bugged Out as he welcomes industry veteran Tom Fitzpatrick to explore the transformative power of AI in functional verification.
In this episode, Tom, author of the whitepaper “Better Stimulus Generation Through AI,” delves into how Questa One Portable Stimulus Assist is revolutionizing stimulus generation. He compares traditional UVM approaches with the Portable Test and Stimulus Standard (PSS), discusses the evolving skill sets for engineers in an AI-driven world, and shares his vision for the future of verification.
Tune in to understand why PSS is set to become the next major leap in productivity and abstraction for chip verification!
Key Discussion Points:
- Meet the Expert: Harry introduces his long-time colleague, Tom Fitzpatrick, highlighting his extensive contributions to the Verification Academy, DVCon US, DAC Executive Committee, and key industry standards like SystemVerilog, UVM, and the Portable Test and Stimulus Standard (PSS).
- UVM Stimulus Generation: The Challenges: Tom explains why traditional UVM stimulus generation can be cumbersome and error-prone, especially as designs scale. Using an example of loading data into memory and performing a DMA transfer, he illustrates the complexities of managing constraints and relationships between UVM transactions.
- The Power of PSS Actions: Discover how PSS’s “action” concept simplifies stimulus generation. Unlike UVM transactions, PSS actions are self-contained, defining their own input and output requirements (like buffers). This allows tools like Questa One Portable Stimulus to automatically connect compatible actions, simplifying complex test scenarios and enabling the generation of diverse test implementations with ease.
- AI’s Impact on Engineer Skill Sets: Harry and Tom discuss whether AI-driven tools will shift the focus from low-level implementation details to higher-level verification intent. Tom emphasizes that while AI can handle many low-level tasks, a deep understanding of the system, correct behavior, and the ability to ask the right questions will remain crucial for verification engineers. He believes the core skill of “what it means to actually verify a chip” will always be necessary.
- The Future of Functional Verification (5 Years Out): Tom predicts that the Portable Test and Stimulus Standard (PSS) will become the dominant solution for system-level testing, achieving the “70% answer” status that UVM holds today. He sees AI accelerating this adoption, providing a “leap in productivity and abstraction” akin to how RTL and synthesis transformed gate-level design.
Resources Mentioned:
- White Paper: “Better Stimulus Generation Through AI” by Tom Fitzpatrick.
Bugged Out
Every chip has bugs — the real question is how fast you can find and fix them. Bugged Out is the bite-sized podcast where we shine a light on the art (and science) of functional verification.
In just 10–15 minutes per episode, host Harry Foster, Chief Scientist, Verification, Siemens EDA, sits down with leading innovators, engineers, and researchers to talk about what’s shaping the future of verification — from AI-driven tools to design-for-test, coverage closure, reliability, and more. Expect candid conversations, practical insights, and a few “war stories” from the trenches of debug.
Whether you’re a verification engineer, a design lead, or simply curious about how we “get the bugs out” of the chips that power our world, Bugged Out delivers focused, informative conversations designed to fit your busy schedule.
