The wire problem: Why advanced packaging is the only answer left as Moore’s Law runs out

Tova (00:00.000): Welcome back to the 3D IC podcast season three. I’m Tova Levy and this season we’re mapping the 3D IC ecosystem from multiple angles. We’ve explored the foundational technologies and even delved into the critical world of hardware security. Today, we’re shifting our focus to a company that’s not just talking about the future of advanced packaging, but actively building it, NHanced Semiconductors. My guest today is Bob Patti, President and CEO of NHanced Semiconductors, a company he established to advance 2.5D and 3D technologies, chiplets and advanced packaging. Bob is a recognized pioneer in the field, holding 21 US patents in semiconductor technologies. Bob, it’s a pleasure to have you join us.

Bob (NHanced Semiconductors) (02:00.000): It’s great to be here.

Tova (02:10.000): So, NHanced is well known for its foundry agnostic approach. Can you elaborate on what that means, the challenges and the opportunities that this presents when integrating chiplets or dies from various foundries into a single 3D IC package?

Bob (NHanced Semiconductors) (02:35.000): Well, NHanced very much looks like a typical semiconductor manufacturer. If you went into our facility, it looks like a CMOS fab. The difference is we don’t build transistors. And that allows us to be really agnostic as to the semiconductor vendors. We look a lot more like an OSAT than a competitor. And that’s very important. When you do 2.5 3D integration, really any advanced packaging, you get a little deeper into how the semiconductor devices are manufactured. We need to know something about the materials used and some of the layer thickness information and this can start touching upon some of the special sauce as far as a manufacturer may be concerned. We certainly are going to know some other things about perhaps the yield of the devices for instance.

Bob (NHanced Semiconductors) (04:00.000): And semiconductor manufacturers, the foundries, are sensitive about this. So it’s very important that we not be viewed as a competitor, but we also are very knowledgeable in it. We understand what they’re building. And we’re neutral, meaning that we don’t treat any of the fabs differently. We take material from virtually all the large fabs. I like to say I think we’ve taken material from every fab in the world at this point. And we’re considered a trusted entity that they can share the information that we require in order to achieve the customer’s goals.

Tova (04:55.000): So the role of a specialized packaging house like NHanced has evolved from being just a backend service provider to becoming a critical partner in the overall chip design and manufacturing system. So can you explain a little more about how that has changed and why?

Bob (NHanced Semiconductors) (05:25.000): Well, one of the big things that’s changed over time is the level of integration that goes in the back end. If you go back 10, 20, 30 years, packaging was almost completely isolated. I mean, the concept of co-packaging kind of came into existence maybe 30 years ago now, but it was almost never exercised by the customers. They didn’t really look at what are the critical things in my assembly path, but as things have shrunk and we’re now doing things really at the same scale as is being done in the front end foundries. We’re now at the micron scale and some things are now moving towards the sub micron scale. It has changed. There is a higher complexity. But it has really attacked the primary reason that the customers now want to use advanced packaging and that’s the wiring. It is bringing components into much closer proximity. That reduces both delay and power.

Bob (NHanced Semiconductors) (06:55.000): Scaling over the last 40, 50 years of Moore’s law has done fantastic things. However, scaling has not helped wire. Wire gets worse as you make it smaller. Transistors get much, much better. And over the last 15 years, it has really culminated in where wire is now the problem. It represents perhaps 95% of the power being used and 95% of the delay in much of the circuitry. So the reason it’s become front and center is because advanced packaging and specialized packaging in general is now addressing the big problem in semiconductors, which is speed and power.

Bob (NHanced Semiconductors) (07:50.000): NHanced has been working in this area for more than 20 years and we’ve pioneered a lot of the industry learning. I would say that us and our partners in it have paid a lot of the tuition of learning how to do advanced packaging and really shrink the world of wire bonding to now where we’re doing intimate connections that are at micron scale between devices. And it has reduced power by perhaps a factor of a thousand in the interconnect between devices. It also allows us to do really this huge, monumental change in the industry by bringing heterogeneous materials and processes from different foundries, different manufacturers together. And this can give you order of magnitude type improvements basically in a single generation of device improvement.

Tova (09:10.000): And now to bring all of that to market, you need a very tight ecosystem, right? With close collaboration. So beyond your direct customers, who are the most crucial partners that NHanced collaborates with? Whether it’s EDA vendors, material suppliers, test houses, even other packaging players. What does it take to bring a complex 3D IC design to life?

Bob (NHanced Semiconductors) (09:50.000): Yeah, certainly semiconductors. We’ve arrived at it takes a village. It really is a tight collaboration from the customer and their design work and IP vendors on that end to the foundries, the advanced packaging houses such as ourselves, the final assembly companies out there and test planning and execution of tests. And of course, the EDA vendors are gluing this all together. They’re a critical partner in all facets of this because the stakes are high.

Bob (NHanced Semiconductors) (10:50.000): Even though I would say advanced packaging and 3D integration is pretty economic compared to the cost of semiconductor devices today, we’re often incorporating devices which are in the single digit nanometer regime. So many of these programs do involve budgets that are pretty large and mistakes are expensive and they take probably more importantly, it takes time to correct them. So the EDA vendors have played a critical role and their role moving forward is becoming more critical because we are moving into an era where the need to design rule check and LVS interconnect check is very important, but now thermal issues and stress mechanical issues and mechanical fit are also equally important because if the parts don’t fit together, it’s really bad to find that out after you’ve perhaps spent millions or tens of millions of dollars.

Bob (NHanced Semiconductors) (12:05.000): So the EDA vendors and especially I’ll point out Siemens here have really been doing significant work to develop new tools and push forward this concept of assembly development kits or assembly design kits which will pull together really many of these facets and then working with the PDKs, you plug in, test and it’s a village.

Tova (12:50.000): So you mentioned the collaboration with Siemens. So can you elaborate a little more on that?

Bob (NHanced Semiconductors) (13:10.000): Certainly Siemens, other than being one of the largest EDA vendors is really at the forefront of advanced packaging. More than any of the other providers, they really have thought through everything that is required to do advanced packaging and what goes into building an assembly design kit, ADK. You need strong stress mechanical modeling, thermal modeling, and these are areas that I think Siemens has done great work and pioneering effort. Their work in 3D, DRC, and LVS with Calibre dates back more than a decade. NHanced has been a long-term user of Calibre 3D, and it is a cornerstone to building advanced package devices. The EDA is really critical for wide scale commercial adoption. Because without it, you have to have your own dedicated team.

Bob (NHanced Semiconductors) (14:45.000): And we have done this for many years. NHanced has been doing advanced packaging for more than 20 years. You can do it, but it has required deep expertise and a lot of additional time to customize things and do your own tools and scripts. Fortunately, Siemens and other EDA vendors, but Siemens much more out front, has been developing the tools and the support that makes this reasonable for average designers to take on doing advanced packaged 2.5 and 3D devices.

Tova (15:40.000): Right. So advanced packaging is often perceived as not only complicated, but also very expensive. So how is NHanced working to make 3D IC and advanced packaging solutions more accessible and cost effective, especially for startups or companies with lower volume, specialized needs? What are the key drivers for reducing the barrier to entry?

Bob (NHanced Semiconductors) (16:15.000): Well, first of all, I’d say that it is very cost effective if you look at it versus doing anything at a leading-edge node. People sometimes are surprised by the cost of advanced packaging because they think of it or look at it through the lens of typical flip-chip assembly, for instance, or even wire bonding. And certainly advanced packaging is more expensive than that because it’s really a foundry process. It is like building an integrated circuit in many cases. It could imply building, for instance, silicon or glass interposers, and the 2.5 3D bonding assembly is done at very fine pitch with foundry equipment and masks and materials. So, yes, it is more expensive, certainly, than traditional packaging, but it is far less expensive than being forced to go to a smaller geometry with your device. And the gains that you get are much higher. You can use mixed materials, exotic processes, and you often get more than 10x improvements in specific market spaces.

Bob (NHanced Semiconductors) (17:45.000): The performance and power gains that you get are substantial. And I think, directly speaking to the cost and challenges, the way that we are making the cost more approachable is we do handle MPWs from some foundries. So it doesn’t require dedicated silicon. 10 years ago, the only choice was dedicated silicon runs. But the advent of chiplets is also changing the economics. Now, chiplets are still pretty rare and a lot of them are siloed, but that’s growing. And as chiplets come into the mainstream, I think we’re going to see a dramatic change in the industry. It’ll be much more like designing a printed circuit board with the VLSI type technology chips that we would have seen in the 80s and 90s. The barrier to entry will be significantly lower. This will, I think, enable a renaissance and resurgence in our industry. It allows risk-taking because now perhaps you can be a startup and be funded by a VC for millions or very small tens of millions of dollars and enter new market spaces because the economics allow it and because of the economics people can take risks. And risk taking is a fundamental requirement to enable growth in the industry and enable innovation in the industry.

Bob (NHanced Semiconductors) (19:35.000): It is going to reduce complexity from the user standpoint as they integrate chiplets. And they reduce the amount of custom circuitry they may have to do. So the cost of their programs will be reduced. The learning and tuition investment that has occurred in the industry ultimately reduces the cost to the broader customer base.

Tova (20:20.000): So let’s say you’ve convinced a designer to go for a 3D IC or advanced packaging design now, because the gains seem to be quite clear from what you’ve explained. So what kind of advice would you give to designers to better design for manufacturability, but keeping in mind the context of advanced packaging?

Bob (NHanced Semiconductors) (20:55.000): Well, from day one you need to have a strong team, good partners in it, people with expertise. And planning for an advanced package really needs to not only touch on design and the foundry, and of course, advanced packaging, what I do, but you really need to think through test. Test can be a huge hidden cost if you don’t think through it. Is this a known good die strategy? Does it have to be? And the assembly and even downstream assembly and the environment it goes in will play some role in the planning. It’s a change perhaps for many of the companies and designers out there because it does require a higher level of planning throughout the entire product development cycle. The stakeholders and various manufacturers need to collaborate early on and make sure that everyone understands their handoffs.

Bob (NHanced Semiconductors) (22:30.000): It’s very hard sometimes to unring the bell in processing. So we want to make sure that everyone knows what’s required and knows what are the critical elements along the way that may be challenges or could be make or break type items in the final assembly. One of the key things if you’re going to do this is understanding what are you doing, what do you get out of it, you need to focus on you’re reducing wire length. What advanced packaging brings to the party, how you get the gains is by reducing wire length. And that wire length will reduce the power and improve speed. It allows you to bring exotic materials closer. So GAN transistors or indium phosphide or MEMS devices for photonics, can bring PIC circuitry close by. That’s reducing the wire. It makes this run faster, use less power. If you don’t exploit these, you’re not going to get gains. And so you’re spending time and effort and money for not a net gain. So you need to be focused on how what you are doing is going to exploit the power of advanced packaging, which is reduced wire length and incorporation of different processes and materials.

Bob (NHanced Semiconductors) (24:35.000): That’s early planning. And it is looking at that. And that really provides other benefits in your product and product development if you focus on those elements. It can reduce the overall complexity significantly. If your choice is doing something with a mixture of chiplets and perhaps a small custom IC versus doing a three nanometer technology device, it can be significantly less expensive, lower risk, much more achievable for the team.

Tova (25:35.000): And so to round this off and also to look a little bit into the future, what do you see as the biggest breakthroughs that are going to be happening in the next three to five years regarding the types of components being integrated? You already mentioned photonics and the complexity of these integrated systems. What sort of new challenges and new benefits are we going to be seeing in advanced packaging?

Bob (NHanced Semiconductors) (26:10.000): Well, first of all, 3D integration and even 2.5D integration, it really is breaking the limits of transistor scaling. We are at the very end of Moore’s law. Even if we ignore the economic consequences that I would say we’ve been suffering under for almost 15 years with increasing transistor cost, the thing is atoms don’t scale. We cannot really make the transistors much smaller than they are no matter what. So we need a new avenue. When you look at the future, what is three to five years out? It is a broader chiplet market. It is more chiplets available in these high performance technologies like GAN. That will allow us to, first of all, create new devices with primarily or entirely off the shelf integrated circuits. That dramatically changes the risk profile and the time to iterate on a design.

Bob (NHanced Semiconductors) (27:30.000): You can almost see some of this today in the cycles of new product releases from the major processor manufacturers out there, which have pretty much all adopted a chiplet approach, where they are able to refresh their product multiple times per year now rather than perhaps every year and a half or so. The other thing that this permits is more targeted designs. And I think this is a tremendous change in the market. It will return us almost to how the semiconductor industry looked in the 80s and into the 90s as ASICs came in to the forefront of the new semiconductor generation, where you could target markets. And in fact, what they were doing is they were reducing transistor count. And because transistors today are more expensive for every one you get, if you can now reduce transistors because you’re targeting a market, you can reduce component cost. And the reason you can’t do that with the shrinks that have occurred is because we have this exponential curve of cost related to building new chips and new circuits and buying masks and really ultimately the cost of factories every time we make the transistors smaller.

Bob (NHanced Semiconductors) (29:10.000): So by the ultimate reuse here with chiplets, targeting applications so that you can take significant number of transistors out. For instance, the average user uses only 30 % of the transistors in their cell phone. If you could now affordably reduce the transistor count, you can actually provide the end customer a Moore’s law cost reduction. And that is probably the most important part of Moore’s Law, is it gave us more for less. And advanced packaging is giving us more for less, and it will do that over the next decade, maybe longer. And in the next three to five years, what we are seeing is traction. The technology has been there. Much of what we do today is not wildly different than what we did five or ten years ago. We’re more practiced at it, certainly. But it is the adoption of it today by the broader commercial and consumer marketplaces.

Bob (NHanced Semiconductors) (30:45.000): Specialty boutique markets have already moved into this area and started to use it because they were forced to for other reasons. Perhaps it was their specific power requirement or physical size. There were other niche applications that have been incorporating advanced packaging and taking advantage of the smaller size footprint, the cost trade off, the customers. The shorter wire length is paramount to the benefits to the end users.

Tova (31:40.000): So if you had to kind of give a message to the overall 3D IC ecosystem within which you’re working for something that needs to be worked on together, what would that be? What would you want to, you know, kind of say to everyone else who’s part of this 3D IC ecosystem?

Bob (NHanced Semiconductors) (32:10.000): Well, definitely one of the things is working through the EDA tools and the ADK PDK flow. We need to do more work in that area. It enables the collaboration, it reduces the risks, and it speeds things to market. The problems are not unsolvable today. But if it takes an extra one, two, three, four months to work around tool issues, that can be the majority of the schedule in a new product development. It’s significant cost and delay in market entry. So I think the collaboration, leveraging the tools that are at hand and exercising them is critical.

Tova (33:00.000): All right. All right. That’s a great message to finish with. And thank you so much for shedding light on the work that NHanced Semiconductors is doing to push the boundaries of advanced packaging and 3D ICs. This has been really interesting for me. And I’m very happy you participated. So thank you for coming on the show.

Bob (NHanced Semiconductors) (33:50.000): Well, thank you very much.

Tova (34:00.000): And thank you all for listening to this episode of the 3D IC podcast. The challenges of integrating diverse technologies, the need for robust collaboration and the immense potential for innovation. These are themes that continue to resonate across everything we’re discussing in this season. Subscribe, share, and stay curious because we’ll be back with more on this season of the 3D IC podcast.