The hidden time bomb: Engineering reliability into 3D IC from day one

Tova (00:00.000): Welcome back to the 3D IC podcast. I’m your host, Tova Levy, and this season we’re taking a comprehensive look at the fascinating and complex world of the 3D IC ecosystem. From design innovations to manufacturing challenges, we’re exploring every angle of how these incredible technologies are shaping the future of electronics. Today, we’re diving deep into a topic that’s often overlooked but absolutely critical: reliability in 3D IC design. We’re going to talk about the hidden risks, the potential pitfalls and how we can ensure these advanced chips stand the test of time. It’s a multi-layered challenge that touches on physics, material science, and human collaboration. So let’s get started. Our guest today is Andras Vass-Varnai, Solution Architect for 3D IC reliability at Siemens EDA. Welcome Andras.

Andras Vass-Varnai (Siemens EDA) (02:05.000): Thank you, Tova, for having me. It’s good to see you.

Tova (02:15.000): You too. So can you tell us about your role and your industry background?

Andras Vass-Varnai (Siemens EDA) (02:30.000): Absolutely. So I work in Siemens EDA. I’m with the company for about 20 years now. I actually started in Flomerix, which is a company Mentor Graphics had acquired back in the past. And Flomerix used to do thermal simulation and actually even had a physical measurement arm called Mikrad, which was a company out of Hungary. And that’s where I started. And over the years I’ve had various roles. Mostly studied application engineering, long time in product management. And currently with the advent of 3D IC technologies, I took a new role, which is a solution architect for figuring out the reliability and how to incorporate reliability into the design of advanced package architectures.

Tova (03:45.000): Alright, so our first question is about the fundamental difference between traditional chip design and the cutting edge world of 3D ICs. When we talk about reliability in traditional 2D chip design, designers follow design rules and the component is basically considered reliable. Why is 3D IC different and why is reliability now everyone’s problem?

Andras Vass-Varnai (Siemens EDA) (04:15.000): So when it comes to traditional packaging, 2D architecture, single die architectures, reliability is pretty much embedded into process rules. So if you follow the process rules and design rules, then likely the output will be reliable, your manufacturing will be reliable. Obviously there are still multiple teams working together or typically working in silos, they don’t really know they work together, but at the end of the day, by creating these design rules, they will make sure that whatever the output is, is either reliable or at least manageable at the end of the design process. 3DIC is a little bit different, so for a 3DIC package, there are just so many different design choices, even for the same packaging technology which a company may choose upfront.

Andras Vass-Varnai (Siemens EDA) (05:15.000): So to make sure that the design will be reliable at the end of the design, you can’t actually just run a final verification check. You need to incorporate design for reliability early in the design process. And this is really because of all the choices you can make. You are making choices on how do you stack your dies, how do you create your floor plan, what materials are you using. Talking about reliability, very often thermal management is the entry point into reliability. So what kind of cooling choices are you going to make? What kind of interconnect technologies are you going to work with? Like what can break within the stack even? So the designs are becoming so complex that you just can’t go by simple rules anymore because it becomes extremely difficult to come up with those rules in the first place.

Andras Vass-Varnai (Siemens EDA) (06:15.000): What we recommend you do instead is make sure that reliability is one aspect of the entire design process. You start checking for reliability from the early phase when you’re creating your 3D IC or 2.5D IC package architecture. Make sure that your early assumptions make sense, they check out, and then as you keep evolving the package model, you get more and more data, more and more information. At every step, every major step, make sure that you run these either thermal or thermomechanical reliability checks. And if you are satisfied with the outcomes, it’s very likely that by the end, when you come to the final sign-off, you will be getting things right. Now if you do otherwise and you make a major mistake from the beginning, it actually gets very, very costly, very expensive to take a couple of steps back and make those changes because likely they will impact multiple other disciplines within the design. So try to simulate early, make considerations early, and then likely you will not have any issues later.

Tova (07:40.000): Yeah. Yeah. So what you said is is I think it’s true for most aspects of 3D IC but let’s get into the physical realities of a 3D IC, right? There is the concept of mechanical stress within 3D IC and the way that that works, you know, across a stack of dies. So can you walk us through how that constant thermal expansion and contraction between stack dies, how does that you know, how does that lead to cracks or you know, other types of wear years down the line?

Andras Vass-Varnai (Siemens EDA) (08:10.000): So that’s a great question, Tova. To answer this, maybe let me take one step back. Because typically when people look at reliability, one of the major contributor or major indicator they like to deal with is temperature. I guess it’s because simply temperature is easier to measure and in some cases also easier to simulate, although you can definitely go down in the weeds and then make the simulations very complex. But temperature is often considered as the lead indicator for reliability. And the reason for that, just to directly answer your question, is that the main culprit behind reliability problems is CTE, which is coefficient of thermal expansion. So different materials have different CTEs and with the different rates of expansion.

Andras Vass-Varnai (Siemens EDA) (09:10.000): So if you create stacks of materials and in a 3D IC that’s what we’re exactly doing. So you know for a typical structure you can have a solder based interconnect on a PCB then you have another organic substrate which is your package base then you have another interconnect layer often solder then you have maybe a silicone interposer hybrid bonds a couple of dies and then not to mention the cooling structure on the top with the themes, the lead and the heat sink. So all of these components may have different CTEs. And even if they don’t, even if they were made of the same material, there will definitely be a temperature gradient which kind of creates a similar effect.

Tova (09:50.000): Right. Yeah, but like the layers the layers in the middle would be hotter than the ones on the outside, right?

Andras Vass-Varnai (Siemens EDA) (10:05.000): Yeah, so the layers which are closer to the heat source, transistors will be hotter and then the heat will propagate. Definitely two ways, one side is down towards the PCB and the other one is typically up, like in a chimney towards the cooling solutions. So there are certain ingredients to manage.

Tova (10:25.000): That’s the exact opposite of what I was saying of what I thought. But yeah, it makes sense.

Andras Vass-Varnai (Siemens EDA) (10:35.000): No, it’s actually depends on how you engineer that cooling path. But you’re absolutely right when you say that there are temperature differences. And even though material engineers do their best to come up with materials with smaller CTE mismatch, I mean, the world is still not ideal. And the problem is as these materials expand and contract at different rates, ultimately warpage will develop within the component. And if that warpage keeps happening, some of the material parameters are so called viscoplastic, which means that when you release the stress, they actually accumulate a small deformation. If you keep doing this, keep exposing the component to various heating and cooling cycles one after the other. Ultimately that strain field just becomes high enough for the component to crack or to delaminate. And actually that’s when typically a reliability problem will ultimately happen.

Andras Vass-Varnai (Siemens EDA) (11:50.000): So it all comes down at the end of the day to temperature, temperature gradients, temperature differences. As during operation, sometimes even during the manufacturing process, you keep exposing the component to these temperature cycles, you are actually very often accumulating damage, especially when it comes to the solder and solder type interconnects.

Tova (12:30.000): Okay, so physical stresses are obviously a major concern, but let’s talk also about the design choices, right? For example, a design team could make a perfectly rational choice to optimize for performance. Let’s say placing chips as close together as possible to improve signal speed, but unknowingly they create a reliability time bomb. So how can how common is this and what does it look like in practice?

Andras Vass-Varnai (Siemens EDA) (13:05.000): Well, I think since 3D ICs or advanced package architectures are there and we’ve been working on this as an industry for quite some time, at least in the R&D phase, what really changed now is that these packages are commonly in practice. But to your question, yeah, you may want to optimize for performance. So as you bring chiplets as close to one another as possible, you get shorter interconnect lengths, better signal integrity, lower latency, even a little bit better power integrity too, because you have less losses. But if you do that, not only you’re bringing components closer, but in modern architectures, often you’re stacking components on the top of one another. And from a thermal perspective, what you’re really doing is you’re stacking power density. So actually, putting more and more power into smaller and smaller volumes, which is the arch enemy of thermal management.

Andras Vass-Varnai (Siemens EDA) (14:10.000): And with that, we get all the thermal gradients we’ve been talking about. And those will actually start triggering these mechanical issues. So as a designer, you can’t just focus on your domain anymore. You can’t just say, okay, I’m trying to fix the single integrity problem or I’m trying to fix the thermal problem because these things are very often or most of the time concurrent. What you need to do instead is approach it as a multi-domain problem, multi-domain challenge. Either make sure that teams work together, they are aware of each other’s design requirements and collaborate or nowadays, more often just work with multidisciplinary design space exploration tools. So make sure that you take a design, you create different derivatives of different digital twins, maybe one electrical, one thermal, one electromechanical, and explore the design space such that you develop an understanding of what the best or most optimal design choices or combination of design choices would be.

Tova (15:30.000): Right. So you have to strike that balance between all of these different considerations. So yeah, so let’s talk about interfaces, right? So 3D IC stacks they rely on interfaces. You’ve got solder joints, hybrid bonds, thermal interface materials, you know, holding everything together and keeping it cool. How do these interfaces age differently than what we see in traditional 2D packaging? And what are the implications when they start to fail?

Andras Vass-Varnai (Siemens EDA) (16:10.000): I would say at the first glance, the problem is very similar to 2D actually, but one thing is for sure. So typically failures don’t really happen in bulk materials. It’s very, very rare. Failures typically happen at interfaces. And you mentioned a few of them. So maybe just to go through those. When it comes to solder type interconnects, so for example, micro bumps, which are very, very common. Typically from a thermal mechanical perspective, this could be the weakest link in the stack because during the operation of the component, you are actually subjecting these to thermal cycling. And we spoke about creep earlier, or the accumulation of stress, and essentially the behavior of physical plastic materials. Solders are typically such types of materials. So once they are exposed to cyclical stress, ultimately, of course, depending on the accumulation of creep in every single cycle, ultimately there will be a limit and these interconnects will fail.

Andras Vass-Varnai (Siemens EDA) (17:35.000): So very often when I speak to our customers, one of the questions they ask is, can we estimate, can we calculate how long a certain solder type interconnect would last in a specific application? Because ultimately the lifetime is also a function of the temperature gradients, which heavily correspond to how the component is operated and what loading or admission profiles are used. Now, there is another very common interconnect nowadays called hybrid bonding. Some of my colleagues often say that hybrid bonding is really the enabler for advanced packaging because you have a very fine pitch high density interconnect solution which you can realize this way. Hybrid bonds are different from a global perspective than solder type interconnects. Because essentially hybrid bonding is a metal and oxide to metal and oxide connection. And once you do this correctly, you are almost combining two materials into one, for the lack of better words. Actually you are creating an extremely strong interconnect, which shouldn’t fail or even if it fails it would take maybe a couple of orders of magnitude higher operational cycle count than solder-based interconnects. So solder still stays the weak link.

Andras Vass-Varnai (Siemens EDA) (19:00.000): However, the interesting thing about hybrid bonding is reliability is not that much of an operational issue. It’s more of a manufacturing issue. So the actual long-term reliability of the hybrid bond depends more on how it’s manufactured, is the alignment correct? Is the surface clean, are the surfaces rough or actually can the bond develop properly? Because once it does, it will likely not fail. An interesting dimension also thermal interface materials. So thermal interface materials are used to help mitigate the thermal challenges because normally if you connect like two different types of materials on the top of each other, even if these are polished and highly flat and parallel. According to textbooks, approximately 80 % of the surfaces will not touch. And that’s simply because of surface roughness, even though that’s on the micro scale. So the reason why that’s a problem is if there is no connection, then you have air gaps in between.

Andras Vass-Varnai (Siemens EDA) (20:20.000): And air is a very well known strong thermal insulator. Just to keep some numbers, typical air thermal conductivity is I think 0.026 watt per meter Kelvin. Now, if you use a very average, I would say nowadays low-end type of the material, that’s somewhere on the lower end, like one to five, on the higher end maybe five to 10 or even 10 plus watt per meter Kelvin. So if you compare that to 0.026, that’s a major, major improvement. So the materials are important, but if they don’t work correctly, if the connection is not good, then it’s like they weren’t even there. In fact, problem can even be worse because they have a thickness. So the gap can actually be bigger than not having TIMs. So you need to make sure that TIMs are reliable. And companies making TIMs, they do their best to try to ensure this reliability. And they do a lot of measurements and simulations, making sure that for cyclical loads, these TIMs will operate well.

Andras Vass-Varnai (Siemens EDA) (21:25.000): But common failure modes are for grease type of TIMs, dry out or pump out. Dry out may happen also for gap pads. And recently people are shooting for even much better TIMs, liquid metals. Metals have a lot higher thermal conductivity coefficient. But sometimes those liquid metals may just kind of flow out from between the surfaces. So they have to be really engineered correctly to stay there. And one of the famous console manufacturers had actually this problem. Maybe those in the audience who do any gaming, there’s a console which if you stand it up vertically versus horizontally, if it’s vertical, the reliability is lower because ultimately the material will flow out. I think it got fixed. That was an issue with the first generation. All of this is just impacting chip temperature.

Tova (22:45.000): Wow.

Tova (23:00.000): Right, so we’ve spoken about materials, physics, the thermal cycles, what about the people involved, right? In a world where 3D design spans multiple teams, time zones, companies, how do the organizational silos and communication breakdowns become a reliability risk of their own kind?

Andras Vass-Varnai (Siemens EDA) (23:35.000): Overall, not every reliability problem is just physical, as you were very correctly pointing out in your question. Part of this is organisational. I think the background for this is, if we take a step back just to our first discussion point, traditionally companies are used to operating in silos. For simpler architectures, this used to work. As we discussed, the reliability aspect was pretty much built into the design rules and manufacturing rules. Now, we can’t really do this anymore and organizations need to, and they have realized it, they just need to figure out how to do things differently in the future. So the typical silos are, there is typically a package design team which needs to work with teams looking into electrical simulations such as signal power integrity or thermal simulations or even thermal mechanical simulations which has never been very common. It’s something I see more and more frequently being addressed.

Andras Vass-Varnai (Siemens EDA) (24:50.000): And as these disciplines are tightly connected, it’s extremely important to make sure that the data is correctly exchanged between teams. So just to give you an example, if you want to create a thermal model for a package design, first of all, you need to ensure that the model is correctly built up from a physical perspective. So you are representing exactly the same die stack, which is being designed, you are using the correct material parameters, and you’re using the correct power, for example, which the electrical analysis team would provide. And it’s not obvious that this is how things happen because A, these teams, they speak a different language. So the thermal engineer has a slightly different perspective than the electrical design engineer or simulation engineer. The mechanical discipline is very different. So it’s not given by default that these engineers, understand each other very well.

Andras Vass-Varnai (Siemens EDA) (25:55.000): Also the data needs to be managed. So if I try to run a simulation, which for example, takes the correct package floor plan and layout, but the materials are not correct, they are from an earlier iteration or the power values are not sufficient, then the simulation outcome will be wrong. It will just predict something else than what I’m actually interested in. So making sure that these different teams are organized and are communicating well is very important. Nowadays, or this is a challenge I see all the time, somebody will do a package design and even though they understand everything I just said, the need for correct data, very often the communication still happens in email chains. Maybe somebody would create a PowerPoint specification or a VZO specification and let’s say you send it over as an electrical package architect to a thermal engineer, then you don’t really have control on what the thermal engineer is doing and you really need to make sure that he or she has access to the latest data. Plus it takes some time to rebuild that model from scratch. And that also is a process where errors can come into the system. The siloed approach is actually very dangerous and it also slows down the entire design for reliability type of procedure.

Tova (27:40.000): Right. So given everything we’ve discussed, stress, aging, thermal traps, the human silos, what’s a modern proactive approach to 3D IC reliability? How can simulation software like those that Siemens offers help teams get ahead of failures?

Andras Vass-Varnai (Siemens EDA) (28:10.000): I think the answer is really digital threads and digital continuity. And what that means is if a design team creates a package architecture, you could consider that as an electrical digital twin of the package. Now, if you do it in a way in a proper packaging tool like in our case, we have created that solution which we like to call that advanced packaging cockpit called Innovator 3D IC Integrator. That toolkit or a proper packaging toolkit should be able to handle all of these different design disciplines which I mentioned in a connected fashion. So, for example, if you design a package floor plan and stack up, you should be able to convert that directly from your cockpit into either a thermal or a thermomechanical model or as a matter of fact, an electrical model. And all of those should be done in an interconnected way. So that’s how you create digital continuity.

Andras Vass-Varnai (Siemens EDA) (29:30.000): So for example, if you have the same input, you create a power simulation. You plug that into your thermal tool, is also called from within the cockpit. It will be leveraging all the information which is there. Specifically on the geometrical side, you don’t need to phrase an email and send it to a colleague manually anymore. You just simply turn your package design into a thermal model, plug in the parameters your colleague is working on or working with, and come up with the thermal field. And then use that thermal field to either feed back to the electrical team, because some of the electrical simulation output is temperature dependent, or move it forward to the thermomechanical team. And with this, everybody is really working based off of the same initial, let’s say golden digital twin of the component. So that’s, I think that’s step one, making sure that you have a nice interconnected design system, which from a persona perspective, a package architect can either handle on his or her own or at least oversee collaboration between different teams as we discussed.

Andras Vass-Varnai (Siemens EDA) (30:50.000): Step two could be, because many of these components, interestingly, we built in advanced packaging are at the end of the day used for AI or machine learning. So why couldn’t we use the same hardware we have built automating some of these solutions? So step two could be allowing these tools to, as we talked about this earlier a little bit, explore the design space. So when it comes to like concurrent problems, as we mentioned, signal power and thermal, we could use the same cockpit, create automatically these derivative views, use automation to explore the design space for a better understanding from a package architect’s perspective, but also have the software offer optimum or optimal solutions.

Andras Vass-Varnai (Siemens EDA) (32:00.000): So from design space exploration and optimization, we can actually go to step three, which is full automation. And that’s where we can leverage AI technology, actually AI technologies. One potential option to do things is using, for example, large language models to create a gateway to communicate with the system in a natural or human language where you create your specifications and tell the system what you would like to design and simulate. Then leverage agentic AI which could run various parts of the flow starting from designing and building the package, package model, creating the different derivative views such as SI/PI, thermal or stress. And based on learnings from the earlier DSE or Design Space Exploration runs, if you have the data available or earlier design data, the tool could even suggest potential best or optimal architectures from the get-go, so you don’t need to waste time on exploring the design space again.

Andras Vass-Varnai (Siemens EDA) (33:35.000): And if we can do this, if we can get to step three, this is something we are heavily working towards. We believe workflows can help with reliability problems on their own, so they are connecting engineering teams. But if we can go to full automation, that could be an exponential increase in productivity, which we would like to deliver to our customers.

Tova (34:10.000): Mm-hmm. Right.

Tova (34:25.000): Sounds like a dream. So yeah. So if you had to give one message to design teams regarding reliability, what would that be?

Andras Vass-Varnai (Siemens EDA) (34:50.000): I would say breaking down silos is the most important thing. Connecting among teams, doing things differently than before would be one key message. But the other one is because of the nature and the complexity of the problem, do not treat reliability as an afterthought, something which you just do at the very end of the design process. But do it differently and consider reliability, both thermal and thermomechanical challenges from the start of the design, from the creation of the architecture of the package. And continuously as your available data increases, as your design gets more and more mature, just rerun these different kind of simulations for reliability and make sure that you’re still on the right path. Because if you’re not, you want to know that as early as possible.

Tova (36:00.000): Right. All right. so we’ve covered a lot today from the fundamental differences in 3D IC reliability compared to 2D, to the critical role of material science, design choices, and team collaboration, which you just highlighted as a major point. It’s clear that ensuring reliability in the 3D IC ecosystem is a complex and multidisciplinary challenge. But with the right tools and a proactive mindset, we can build a more robust and reliable future for these incredible technologies. Thank you so much, Andras.

Andras Vass-Varnai (Siemens EDA) (36:55.000): Thank you for the conversation. I really enjoyed it.

Tova (37:10.000): So to our listeners, thank you for joining us on this deep dive into 3D IC reliability. Join us next time as we continue to explore the fascinating world of the 3D IC ecosystem. Until then, stay curious and we’ll see you in the next one.