Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC

Tova (00:00.000): Welcome to season 3 of the 3D IC podcast. I’m Tova Levy and I’m excited to be stepping in as your new host for this season. If you’ve been with us since the beginning, you know that the previous seasons have done a fantastic job of getting into the technology itself, the physics, the design challenges, the tools. This season, we’re pulling back the lens to look at the bigger picture, the 3D IC ecosystem, because here’s the thing, 3D ICs don’t exist in a vacuum.

Tova (00:00.000): Building them requires an intricate web of collaboration between IP providers, chip architects, EDA vendors, foundries, packaging specialists, security experts, and so much more. And that ecosystem is still very much taking shape. So this season, we’re going on a journey to understand it, its current state, its growing pains, and where it’s headed. To do that, we’re doing something a little different. Yes, you will still hear from brilliant Siemens experts, but we’re also opening the doors wide to customers, partners and collaborators from across the industry. The people who are living and breathing this ecosystem every single day will be asking the hard questions. What’s working? What’s broken? What does it take to make 3D ICs not just technically possible, but commercially real?

Tova (00:00.000): And what better place to start than with the IP layer? Because before you can stack dies, integrate chiplets or push data across a high bandwidth interconnect, someone has to design the silicon IP that makes all of that possible. And that is no small feat. My guest today is Archana Cheruliyil from Alphawave Semi, a company at the forefront of high-performance connectivity IP, and one that has been navigating the very specific, very real challenges of developing IP optimized for 3D IC architectures. We’re going to cover Alphawave’s role in the 3D IC enablement story from UCIe and HBM IP to chiplets, photonics, and the real integration challenges around signal integrity, power integrity and thermal management. And we will tackle the market side too. The friction, the standardization debates and how you strike the right balance between cutting edge performance and the demands of reliability, testability and time to market. It’s a packed conversation and the perfect way to kick off the season. Let’s dive in. Welcome, Archana. I’m very excited to have you on our podcast.

Archana Cheruliyil (Alphawave Semi) (02:17.000): Thank you for having me, Tova. I’m really looking forward to this conversation.

Tova (02:32.000): Me too. So let’s start off with yourself. Tell us a little bit about your background, how you started out in the industry and what your role today is.

Archana Cheruliyil (Alphawave Semi) (02:48.000): Sure. So I’ve spent about the last 15 years in the semiconductor IP domain, mostly building high-speed clocking circuits and more recently memory subsystems that enable today’s modern AI systems. I work very closely with our customers to enable their new system architectures as demands have evolved. Over the time, I’ve seen our industry transition from monolithic SoCs to more disaggregated chiplet-based designs and now into the more advanced 2.5D, 3D, and even 3.5D integration. I would say that my day-to-day focus is mostly at the intersection of technology and architecture. So trying to understand what’s needed to enable your next generation of systems. And a big part of that is our connectivity IP, which I would say has evolved more from a supporting function into a critical performance enabler. And I’m excited to talk to you more about the space.

Tova (04:18.000): We will. So tell us a bit also about AlphaWave. How does AlphaWave Semi fit into the 3D IC ecosystem and how is it helping to advance it?

Archana Cheruliyil (Alphawave Semi) (04:35.000): Yeah, so at a very high level, right, if you think about 3D ICs, they are only as effective as the communication between the different dies because now you have disaggregated architectures. So as you move into chiplets and even stacked architecture, your connectivity becomes really important and almost foundational that determines your overall system performance, power efficiency and scalability. Where Alphawave fits is in terms of the interconnect layer, right? We enable high speed, low-power communication across your dies, whether it be within a package or across chiplets. And we’re essentially making sure all of the pieces of these 3D systems work together seamlessly.

Archana Cheruliyil (Alphawave Semi) (05:35.000): So some of the things that we do in terms of the IP domain is one good example is our UCIe, a subsystem. So standards like UCIE are a big part of enabling the chiplet ecosystem. They ensure that different vendors can interoperate, which is critical for scaling 3D IC adoption across the industry. There’s still a lot of work that needs to be done in this space in terms of true interoperability, but the motivation is there. Another key piece of IP is obviously our memory interface, so predominantly our high bandwidth memory, HBM. So this is especially important today for large language models and generative AI, where memory bandwidth is key bottleneck today.

Archana Cheruliyil (Alphawave Semi) (06:35.000): And lastly, I think one of our key differentiators is custom silicon. So beyond standardizing just interfaces, a big part of what we do is also custom silicon, right? So we work closely with our customers to tailor connectivity solutions to their specific architecture needs that helps them optimize beyond what standards alone can provide. So overall, I think we are enabling 3D IC at multiple levels, right? From standards that drive ecosystem and custom silicon that helps customers differentiate at the system level.

Tova (07:15.000): All right. So this is all at the very ideal level, right? But when it comes to actually integrating 3D ICs, there’s a lot of headaches. So can you explain a little bit about that? What are the specific challenges in 3D IC integration that are the challenges for your team or for your customers?

Archana Cheruliyil (Alphawave Semi) (07:35.000): Yeah, I mean, 3D integration provides a lot of architectural flexibility, right? I think everybody’s exploring disaggregated architectures, but it also introduces a whole new class of problems that you don’t typically see with the traditional SOC designs that are monolithic. So a couple of points I think I want to touch upon is one, your signal integrity challenges, right? With much shorter interconnects, you would expect that signal integrity gets better or easier, right? But in reality, what we’re seeing is that your coupling noise, just overall the complexity has increased so much because you have denser routing that you’re dealing with very different electromagnetic environment in the 3D structures, right? So your signal integrity is definitely forefront in all of the designer’s mind when you think about 3D IC architectures.

Archana Cheruliyil (Alphawave Semi) (08:35.000): The other is power integrity, right? Power delivery becomes significantly more complex as you move into 3D stacks, you’re distributing power across not just a single die, but you’re managing it vertically among multiple dies. So you also introduce some challenges around IR drop, noise, stability, all of those become challenges. But I think the biggest challenge of them all, I think, is probably thermal, right? When you stack dies, especially high-performance logic, you could create a lot of hotspots that are much harder to dissipate. Unlike your traditional planar designs, you don’t have straightforward paths for that heat to escape from a stacked architecture. So I think while I think 3D IC does unlock incredible performance, they really force you to think in terms of system level trade-offs across your signal, power, thermal, and of course packaging, right, which is also at the forefront today in terms of how you co-design silicon with package.

Tova (09:45.000): And we’ll talk about those trade-offs later on in this episode. And so when AlphaWave Semi develops IP for 3D ICs, what are some of those unexpected technical hurdles that you encounter that might not be immediately obvious to someone outside the IP design world?

Archana Cheruliyil (Alphawave Semi) (10:10.000): So I guess from the outside, I think IP development might look very modular, right? It’s an off-the-shelf IP that you could license. But in reality, I think 3D ICs are extremely complex. Yes, yes. The complexity is really in how interconnected everything is today, right? To form a seamless die that almost behaves monolithic, but is actually truly disaggregated, right? Which is why I think I spoke about connectivity IP, right, which is one of our foundational pieces.

Tova (10:45.000): Yeah, that’s the dream.

Archana Cheruliyil (Alphawave Semi) (10:55.000): It’s no longer just a data pipe, right? It’s directly impacting your overall system performance, your power, and even workload behavior, especially in the AI space. I think your connectivity IP has become a system critical component. Another aspect is, of course, packaging, right? It’s a less obvious challenge in how tightly coupled your IP design is with packaging, right? You can no longer design your PHY or your interface in isolation anymore. It has to be co-optimized with the package type, your interposer, and sometimes even your stack configuration.

Archana Cheruliyil (Alphawave Semi) (11:55.000): I’ll give you good example, right? So if you think about photonics, there’s a lot of buzz around photonics integration today, right? As we start bringing your photonics chips into the picture, it introduces a whole completely new set of challenges, because you’re coexisting now optical and electrical interfaces, which have completely different materials, different design constraints, all within the same package, right? But because your workload demands are ever evolving, you are having to integrate some of these newer technologies within the same package. So I think a lot of these challenges aren’t just technical, right? In isolation, they come from the fact that everything is so deeply interdependent in the 3D IC system.

Tova (13:00.000): So from your perspective, what are the biggest points of friction or resistance that Alphawave Semi faces when trying to introduce new 3D IC optimized IP to the market? Is it, you know, is it design methodology, inertia, verification complexity? You know, what are what are the reasons for, you know, for this process being so complicated for customers?

Archana Cheruliyil (Alphawave Semi) (13:30.000): Right. So I think you’re right. It’s just not one thing, right? It’s a combination of everything that you mentioned. It’s ecosystem maturity, how complex your design is, and then just the natural inertia that comes when you’re shifting to a completely new architecture paradigm, moving from monolithic to now more disaggregated systems. If you think about the design methodology inertia, I think our teams have spent years optimizing around your monolithic SOC flows. And now when we’re moving to more chiplet-based or 3D IC designs, it kind of requires you to rethink how you partition your system and then how do you integrate that back so it seamlessly works as a single architecture and sometimes even team structures. You’re having to kind of rethink all of these different design methodologies.

Archana Cheruliyil (Alphawave Semi) (14:45.000): And the other thing I think is you spoke about standardization, right, which it’s a double-edged sword, right? So you have standards like UCIe, which are extremely essential for building an ecosystem. But they’re also, in the sense, they do enable interoperability, right? But what we are seeing from customers often is that they want to go beyond the standard to optimize for their specific performance or power targets. So it’s a bit of a double-edged sword while we want to develop to a standard that helps interoperability, right? But they’re not keeping pace in terms of the demands as to how quickly the market is moving in terms of the application demand. So we are walking this tight rope between customization versus interoperability, right? Where we are wanting open standardized interfaces, but also needing highly customized solutions for differentiation.

Archana Cheruliyil (Alphawave Semi) (15:50.000): And that’s something we see quite often in all of our interactions with customers. And I guess underneath all of this is that risk that these are very large, high cost systems. So your customers are naturally cautious about adopting new architectures and IP unless they have high confidence in reliability and scalability. So it’s all of the above, would say. So in terms of the real challenges, I think it’s a combination of your methodology shifting, how quickly your ecosystem is maturing around these new standard interfaces, and how do you balance customization versus sticking to a standard that creates a friction in the market.

Tova (16:45.000): Now you mentioned earlier the need for trade-off, which is also something you just described, like that constant trade-off between things. So how do you balance the need for cutting-edge performance and those demands for reliability, testability and manufacturability?

Archana Cheruliyil (Alphawave Semi) (17:10.000): So I think when you talk about how do you balance, I think it’s really about, it’s a co-optimization problem. You cannot treat your performance reliability and manufacturability as separate goals, right? Especially in 3D ICs, they all have to be thought about and designed together right from the start. Right, pushing for maximum performance, for example, your higher bandwidth, higher speeds, lower power can stress your signal integrity, could increase your power density and make both testing and manufacturing more challenging. Right. So if you’re thinking about it from just performance perspective, the other thing is also your time to market. Right. One of the most common tensions that we see today is your time to market versus robustness. Right. So have you spent the time validating it, going through a couple rounds of test vehicle implementation. So you have high confidence before you do high volume production, but customers want to move fast. And in 3D ICs, the cost of failure is significantly higher compared to traditional designs. So you have to be very deliberate about your validation and what margins you see in pre-silicon.

Archana Cheruliyil (Alphawave Semi) (18:35.000): So that’s where I think testability comes in. So testability becomes that much more important when you have multiple dies on a single package. So we’re seeing new strategies like built-in self-test. We do a lot more test vehicles at Alphawave where all of our IPs are silicon validated before they go into a customer production vehicle. And we’re enabling more and more system level validation, right? So we ensure there is maximum coverage at the system level. Emulation is a big part of that as well, where we are partnering with Siemens, of course, where we try and understand how the entire system behaves, not just individual IP blocks, right? Well before we see any silicon.

Archana Cheruliyil (Alphawave Semi) (19:40.000): And ultimately, I think these decisions show up in the end product as you’re reliable, how efficient you are and how consistent you are, right? So your best systems aren’t always the fastest, but they are the ones, I think, that deliver predictable performance, especially at high volume. So I think it’s more about how you co-optimize all of these different vectors that are often competing against each other. So in the long term, you don’t compromise on either reliability or scalability.

Tova (20:30.000): So if you could wave a magic wand and instantly solve one major pain point for your 3D IC customers, what would that be and why?

Archana Cheruliyil (Alphawave Semi) (20:50.000): I would like to do that. I’m sure my customers would appreciate that as well. If I could solve, I think some of the biggest pain point, I think I’ve had to pick one. I think it would be the ability to have a truly open and interoperable chiplet ecosystem. Today, we are seeing that more and more architectures, not just across data centers and AI and HPC applications, but we’re also seeing some of the emerging markets like automotive, your edge, IOT, mobile, all exploring chiplet-based architectures, right? But the integration is still highly customized.

Tova (21:35.000): Yeah.

Archana Cheruliyil (Alphawave Semi) (21:45.000): If we could enable a truly open marketplace where chiplets from different vendors could seamlessly interoperate with one another, I think it would dramatically reduce your design complexity as well as your time to market, which particularly in some of these industries are very key in terms of how quickly you can get a product out to market. So that kind of interoperability, I think, would unlock a lot more innovation, where your teams can now focus more at the system level of how to introduce more innovation to meet the need of the application, rather than having to reinvent integration every time, which is where we’re spending a lot of cycles today where when you have IPs or chiplets from different vendors, there’s a lot of time spent reinventing integration by our customers. You might wonder what’s holding us back. We do have standards like, I think, UCIe, which is a great step forward, but not quite there in terms of plug and play compatibility across the ecosystem, which I think our customers would appreciate if we could truly reach that stage. I can tell you that there’s a lot of work going on in the industry today to enable this. The motivation is there to enable this. So that’s a good thing.

Archana Cheruliyil (Alphawave Semi) (23:20.000): And if I could pick one more, I think for our customers, I think thermal is always forefront in front of all of our customers’ mind, especially in 3D IC systems. So if we could help remove or help contain your thermal constraints, it would unlock much deeper 3D stacking as well as higher system performance. I think solving either of these would remove a major barrier in how quickly we can scale 3D ICs and how quickly they get adopted across much broader range of applications. So we would, I think, essentially move where we are very integration heavy in terms of how much cycles we spend on it. And we can move more towards innovation around compute, innovation around package, right? And then focus on some of those constraints, not just integration.

Tova (24:15.000): Well, I’d be happy to give you two of those magic ones if it was up to me. And now, so what do you see in the near future, which is bringing that 3D IC ecosystem closer right now?

Archana Cheruliyil (Alphawave Semi) (24:40.000): I think we are at a point where I think few key trends are starting to align, right? And that’s really bringing, I think, our 3D IC ecosystem closer together. One is your standardization, right? It’s gaining traction. Interfaces like your UCIe are very mature today and are seeing very broad adoption across the industry, right? So they’re making it easier, I think, for different parts of the ecosystem to kind of work together, reducing some amount of that integration friction that we spoke about earlier. So I think standardization is great. I think we should continue to work towards that. And along the same lines, we’re also seeing a lot more ecosystem collaboration, right? It’s not just across your value chains, like traditionally your IP providers and foundries and OSATs, but also system companies, EDA vendors, right? We are working a lot more closer to enable these complex systems and almost shift left some of these design methodologies so you can help bring some of these products to market faster. So we’re seeing a lot more close collaboration across different value chain providers.

Archana Cheruliyil (Alphawave Semi) (26:05.000): Another key trend we touched upon this is also some of the newer technologies that are coming online, right? I think photonics is a very exciting area. We will hear a lot more, I think, in the next few years. This is specifically driven, I think, because your bandwidth demands, they continue to right? Whereas, you know, there is a limitation in terms of how much copper can scale while still being power efficient, right? So you’re trying to integrate optical interconnects now right alongside your electrical ICs. And that could fundamentally change, I think, how we think about system connectivity, especially, I think, it’s starting with data center environments. So I think that’s one key technology that we should all watch out for.

Archana Cheruliyil (Alphawave Semi) (27:10.000): And then again, I think, you know, your customized silicon, right? I think in the near future, I don’t see that going anywhere. I think a lot of customers are still, there’s a growing focus, I think, on custom power optimized IP, especially as workloads become more specialized, they’re looking for solutions I think that are tailored to their exact performance and efficiency needs. And I think another pillar is advanced packaging. So we talked about disaggregated systems and as you continue to innovate in advanced packaging, that’s what’s enabling all of these architectures to be more practical and also to be able to manufacture them at scale. So I think advanced packaging, which also ties into the photonics piece, right? That’s essentially enabling your photonics IC and electrical IC to be in the same package. So think overall, I think it’s convergence of your standards, collaboration across your different vendors, and technology innovation that will help accelerate our overall ecosystem forward.

Tova (28:30.000): Alright. Okay. What a way to open season three. Thank you so much, Archana, for such a great look at what IP development for 3D ICs actually involves. And the themes you’ve raised, that need for an open marketplace, the dream of more 3D stacking without the thermal headaches, the tension between standardization and customization.

Tova (29:15.000): Those aren’t just Alphawave’s challenges, they’re the ecosystem’s challenges and they’re exactly the kind of threads that we will keep pulling on throughout the season. And to our listeners, if this episode resonated with you, please share it with your team, your design partners or that colleague who keeps asking why 3D ICs are so complicated. This podcast is for all of them. Archana, thank you so much. I really enjoyed this. This is great.

Archana Cheruliyil (Alphawave Semi) (30:05.000): Yeah, it was a pleasure. Thank you for having me.

Tova (30:20.000): All right. And make sure to subscribe, stay curious, and we’ll see you in the next episode. Thank you, everyone.