Customers Share Their Experiences Using High-Level Synthesis

High-Level Synthesis (HLS) has never been more in demand for chip design. In fact, it could be said that the…

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can dramatically speed up the design…

SemiEngineering: Inference Moves To The Network

SemiEngineering: Inference Moves To The Network

Excerpt from article: “Inference Moves To The Network” Interviews with different players reveal three distinct categories of inference between the…

New Ways To Optimize Machine Learning

New Ways To Optimize Machine Learning

Excerpt from article: “New Ways To Optimize Machine Learning” Some projects are experimenting with larger strides. A stride of 2 means…

Power Is Limiting Machine Learning Deployments

Power Is Limiting Machine Learning Deployments

Excerpt from article: “Power Is Limiting Machine Learning Deployments” The total amount of power consumed for machine learning tasks is…

Providing An AI Accelerator Ecosystem

Providing An AI Accelerator Ecosystem

Excerpt from article: “Providing An AI Accelerator Ecosystem“ A key design area for AI systems is the creation of Machine…