Stanford University: Edge Machine Learning DNN Accelerator SoC Design Using Catapult HLS | Webinar

This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped…

How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar

Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can…

image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

In this blog post, we explore the key points which are required to convert an…

SemiWiki: High-Level Synthesis at the Edge

Excerpt from article: “High-Level Synthesis at the Edge” Custom AI acceleration continues to gather steam….

SemiEngineering: Improving Algorithms With High-Level Synthesis

Excerpt from article: “Improving Algorithms With High-Level Synthesis” Most computer algorithms today are developed in…

Master the design and verification of next gen transport: Part Two – high-level synthesis

Excerpt from article: “Master the design and verification of next gen transport: Part Two –…

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

Excerpt from article: “AI Hardware Summit, Report#2: Lowering Power at the Edge with HLS” I…

Master the design and verification of next gen transport: Part One – overview

Excerpt from article: “Master the design and verification of next gen transport: Part One –…