Excerpt from article: “Improving Algorithms With High-Level Synthesis”
Most computer algorithms today are developed in high-level languages on general-purpose computers. But someday they may be deployed in embedded systems where the development, verification, and validation of algorithms is done in languages like python, Java, C++, or even numerical frameworks like MatLab.
This is the goal of high-level synthesis (HLS), and it aims to solve a fundamental problem in system design today. The basic idea is allowing hardware designers to build and verify hardware, with better control over optimization of the design architecture, describing the design at a higher level of abstraction while the tool implements the RTL. It also may be possible to use HLS to improve today’s algorithms that run on that hardware.
The ultimate description will be in a hardware description language (HDL) at the register transfer level (RTL). So it’s not so much the algorithm that will be affected by HLS. It’s the implementation of the algorithm.
“HLS allows a large variety of architectures to be explored quickly, and enables very different implementations of an algorithm to be created without a lot of coding and without the risk of breaking the algorithm or requiring a lot of verification and debug,” said Russell Klein, HLS platform program director at Siemens EDA.
Read the entire article on SemiEngineering originally published on December 30th, 2019.