What’s new in HyperLynx 2604

Accelerating PCB design with smarter and enhanced workflows

HyperLynx 2604 release brings a comprehensive set of enhancements that make PCB design verification faster, more intelligent, and more accessible. We are thrilled to announce the new AI-Powered Capabilities powered by Product Support Copilot which integrates with Siemens Fuse EDA AI System, providing documentation support directly within HyperLynx SI/PI, Schematic Analysis, Advanced Solvers, DRC, and AMS. This contextual help reduces time spent searching documentation and accelerates the learning curve for new users. This release delivers meaningful improvements across all product lines: Schematic Analysis, AMS, DRC, SI/PI, Advanced Solvers, and Design Space Exploration, with a clear focus on eliminating tedious manual work and accelerating design cycles.

Here’s a quick update on each of these areas:

Schematic Analysis:

Model creation has traditionally been one of the most time-consuming aspects of signal integrity analysis. HyperLynx 2604 transforms this workflow with breakthrough automation features:

• Creating active models from Xpedition Designer now extends beyond passive components and connectors to include any part in the design. The software automatically propagates pin numbers, names, types, and part numbers directly from schematic symbols, creating partially-filled models that eliminate the “starting from scratch” approach.
• Intelligent model editing eliminates reliance on Excel templates entirely. Engineers can now work directly within HyperLynx with features that exceeds Excel’s capabilities.
• Import FPGA model from FPGA I/O Optimizer. Previously, users had to export Xchange files in CSV format; now, I/O Optimizer’s native FCD files import directly, removing an entire step from the workflow.
• Bit swizzling support, is a long-requested feature that allows re-ordering of 8-bit groups (bytes) within wider data buses. This is commonly used to optimize PCB layout, reduce trace length mismatches, and achieve timing constraints.

Analog-Mixed Signal Analysis:

• HyperLynx 2604 introduces Parallel Processing in AMS/DSE Optimization Studies. Building on the DSE integration introduced in version 2510, the 2604 release allows users to set multiple designs to run simultaneously when the DSE environment is invoked, which dramatically increases the speed of the optimization studies.
• Support for Boolean and Integer Ports in FMUs (Functional Mock-Up Units). While HyperLynx AMS 2510 introduced the ability to import and export FMUs using the Functional Mock-Up Interface (FMI) standard, version 2604 extends this to support Boolean and integer signal ports, not just analog signals.

Design Rule Check:

The HyperLynx DRC team focused extensively on quality improvements in the 2604 release, establishing a foundation for future updates and HLDRC transitional opportunities, Creepage Wizard improvements, Product Support Copilot integration, and analysis improvements.

• Delivering on transitional opportunities. The scripting environment native to HLDRC now includes action script support, completing the enhancement process in the transition from classic to modern capabilities.
• Creepage Wizard improvements. Engineers can launch the wizard directly from the HL DRC Application Launcher. The new release brings improved usability, faster access, smarter layers, and clearer rule definition​
• Analysis improvements strengthen critical 4 layout rules without adding complexity, resulting in fewer false positives and, more confident PCB design.
• Product support copilot enhances application support with an AI-driven interface that allows users to query product documentation using natural language.

Power Integrity:

Power integrity analysis receives significant enhancements in visualization,  workflow efficiency, and decoupling wizard report improvements

• DC Drop improvements: the DC Metrics Viewer integrates directly into the post-layout environment, opening automatically after simulation or manually via command bar. The viewer displays key metrics, giving users detailed information for that location. Several usability improvements have been made to both Interactive and Batch DC Drop workflows. And finally, The DC Drop App now supports a Pin Group assignment option for DC Sink models.
• Power Network enhancements enhance workflow efficiency with organized grouping, instant zooming, and simplified visualization that minimizes clutter.
• Power Integrity models dialog improvements add two key features: an “Include attached nets” option on the IC Tab to view all connected Reference Designators, and Pin/Net Name filtering on the Other Supply-Net Components Tab for quickly locating pins on large ICs.
• PDN Time-Domain Analysis Wizard (beta feature) represents a significant new capability. Engineers can apply stimulus at PCB or PKG ports to simulate switching events, verify voltage droop against BGA requirements, and analyze voltage recovery driven by decoupling capacitors.

Signal Integrity:

• General Signal: now, the Sliding Panel Customization gives users unprecedented control over their workspace and further optimize wporkspace icons to their preference. The Touchstone Viewer makes it easy to customize graph properties through an Edit Chart Style window.
• DDRx Interface Design & Verification: the new DDRx Batch Wizard Parallelization Support drastically accelerates full-interface simulations, reducing bottlenecks from days/hours to achieve up to 10x performance gains. Single DDRx license includes 2 parallel simulations at no extra cost; additional acceleration licenses enable seamless scaling for greater speed. Also, Clock forwarding enhancement is now supported in Advanced AMI flow. This means you’re getting it with superior accuracy, capturing driver non-linearities for results far beyond reference IBIS-AMI flows. Additional features include HTML report enhancement, and adding sweep capabilities to BoardSim or post-layout in the DDRx Batch Wizard
• Serial Link (SerDes) Design & Verification High-speed serial link designers receive comprehensive PCIe Gen 7 Support, including configurations for the PCI Express Base Specification Revision 7.0 and PAM4 signaling at 128 GT/s. Also, more configuration updates for PCIe Gen 4-6. Another update to the Multiport Model makes crosstalk‑aware compliance simpler and faster. Lastly, we updated the protocol support and compliance wizard report options.

Advanced Solvers:

• Pin Thickness: BoardSim’s Advanced Port Options dialog now includes Pin Thickness parameter for J-Lead connections, allowing direct modification of metal pin thickness without invoking Advanced Solvers.
• GDSII Performance Improvements deliver 3-10x faster GDSII scanning with improved net/pin/material transfer, and new “Reassign From Properties” feature.

Download the release

The latest release can be found on support center. If you’re not a current customer, contact us for pricing!