What’s new in HyperLynx 2504
The HyperLynx 2504 update introduces a wealth of new features and enhancements that elevate the PCB design process, enabling engineers to tackle even the most complex challenges with greater efficiency and precision.
At the heart of HyperLynx’s mission is the goal to enable simulation earlier in the design cycle, make simulation accessible to a broader range of users through automated workflows, and foster tighter integration with schematic capture and layout tools. The 2504 release takes significant strides in realizing this vision, delivering a suite of powerful capabilities across the HyperLynx portfolio.
Streamlining schematic analysis with automated modeling
One of the key barriers to widespread adoption of schematic analysis has been the challenge of modeling. The 2504 release addresses this head-on with the introduction of a new tool in the Project Creator dialogue, allowing designers to quickly generate passive and connector models based on reference designator prefixes. This feature significantly reduces the time and effort required to set up the necessary models, empowering more users to leverage the power of schematic analysis.
Furthermore, HyperLynx 2504 introduces the ability to import FPGA I/O Optimizer exchange files directly into the Schematic Analysis FPGA Auto Modeler, seamlessly integrating these critical design elements. The release also enables users to connect to multiple model databases, providing greater flexibility and control over their modeling resources.
Enhancing analog and mixed-signal capabilities
The 2504 update expands the versatility of HyperLynx AMS (Analog and Mixed-Signal) by introducing support for Verilog AMS, a hardware description language that combines analog and digital functionality. This broadens the range of models that can be utilized within the HyperLynx AMS environment, empowering designers to tackle an even wider array of design challenges.
Additionally, the new “Import PartQuest Explorer Design” command simplifies the process of bringing designs from the cloud-based PartQuest Explorer platform into the HyperLynx AMS ecosystem, streamlining the design flow and enabling a more seamless integration of tools.
Elevating design rule checking with reintegrated features
HyperLynx 2504 marks a significant milestone with the reintegration of features previously available only in the Classic mode, now accessible through the modern user experience. This includes the integration of the HyperLynx SIPI and Xpedition Layout Stack Up Editor, as well as the script debugger, bringing external automation capabilities to the forefront.
The release also introduces several quality-of-life improvements, such as the addition of a component placement layer to support embedded components, user layers for both Xpedition and Allegro layout flows, and a progress indicator when loading designs. These enhancements contribute to a more streamlined and efficient design review process.
Moreover, the Creepage engine has been vastly improved, with enhanced visualization of creepage violations, support for partially routed nets, and the ability to exclude constant nets based on user preferences. Two new out-of-the-box rules for IC packaging, “Exposed Vias” and “Missing Teardrop,” have also been added, further expanding the design rule checking capabilities.
Advancing signal integrity, power integrity, and DDR interfaces
Across the HyperLynx product suite, the 2504 release introduces a wealth of improvements and new features. In the realm of general signal integrity, HyperLynx LineSim now allows for manual control over wiring segments, enhancing the user’s ability to clean up overlapping wire segments.
In the power integrity domain, the latest updates focus on streamlining the setup and management of power supply nets and components, with features like automatic listing of inductors and ferrite beads, power supply net candidate previewing, and separation of AC and DC resistance parameters. The integration of the HyperPI engine into the Decoupling Wizard also delivers a significant speed improvement for simulating large power nets.
For DDR interface design and verification, HyperLynx 2504 introduces expanded support for DDR5 and low-power DDR5X, including new speed grades and enhancements to the DDRX Batch Wizard GUI. The release also offers a more streamlined simulation control page, improved eye diagram viewing, and enhanced reporting capabilities.
Strengthening enterprise data management integration
Recognizing the importance of seamless collaboration and data management, HyperLynx 2504 introduces several new features to enhance its integration with Siemens’ Enterprise Data Management (EDM) platform. Users can now view PCB version metadata, leverage ODM file support for improved performance, and save their current design and process without a full check-in, enabling better collaboration and time savings.
Additionally, the release allows for the direct export of specific files, such as stack-up files, BOM files, and reference files, without the need to check out the entire simulation data folder, further streamlining the sharing of critical design information.
Unlocking the future of simulation
By introducing a wealth of new features and enhancements across the entire HyperLynx portfolio, this update equips design teams with the tools and capabilities they need to tackle the most complex challenges, optimize their workflows, and drive innovation in the ever-evolving world of printed circuit board design.
