What’s new in HyperLynx VX.2.14
The new VX.2.14 release of HyperLynx contains improvements across:
- HyperLynx DRC
- DDR5 interface design and verification
- Serial Link interface design and verification
- Integration with Xpedition Engineering Data Management
HyperLynx DRC
HyperLynx DRC includes a new via length rule that checks the combined length of vias in a net and improvements to multi-layer creepage rules and acute angle rules.
A new area crop capability speeds checking of complex boards by allowing users to identify a portion of the board to be checked, then creating a new, smaller board to run the selected rules against.
DDR5 interface design and verification
HyperLynx SI now provides system-level simulation for DDR5 registered DIMMs. The DDR wizard has been extended to include support for Registered Clock Devices, or RCDs, present on RDIMMs.
HTML reporting has been improved to include a summary page and consolidate information that previously spanned several tabs.
Serial Link interface design and verification
HyperLynx SI also includes SerDes Compliance support for 9 additional protocols. New ladder filter package models and raised cosine filter support lets HyperLynx verify serial channels based on the latest standards.
The IBIS-AMI simulation wizard has been enhanced to improve specification and management of jitter parameters, ensuring integrity of jitter data provided by the AMI silicon vendor.
Integration with Xpedition Engineering Data Management
Improved integration with Engineering Data Management, or EDM, in HyperLynx VX.2.14 lets you selectively check data into the EDM vault, allowing you to save only the data you really want to retain as part of the project record.
With new features and enhancements across the VX.2.14 release, HyperLynx helps you create, optimize and verify your designs quicker than ever before.
