The importance of basic signal integrity simulations is often misjudged. That’s an odd fact, given that the cost of rework and field failures often can be avoided simply by analyzing designs prior to fabrication.
If you’re ready to ready to reduce those expenses and step into simulation, it’s important to realize that basic signal integrity (SI) issues should be taken into account early in the design cycle. Fortunately, that’s easy to do!
Simply use the capabilities built into PADS Standard Plus or PADS Professional to create realistic constraint values for your PCB design. Pre-route analysis (HyperLynx LineSim) will help you understand the effects of coupling and create a plan for routing noisy nets such as clock nets.
To get a realistic idea of the board’s behavior, you should also perform post-layout analysis on the critical nets. For example, routing a clock net next to a data net can have an adverse effect on the data signal. Using post-route analysis (HyperLynx BoardSim), you can run a quick simulation using batch SI analysis to get an approximate idea of the problematic nets and then use detailed analysis for signal quality, delay, and crosstalk analysis.
For more information on how to use these tools, check out my new webinar, “How to avoid crosstalk and signal integrity issues on your PCB design.” Remember, it’s only through simulation that you can know that your PCB design works!