Designing high-speed DRAM DDR memory busses can be stressful. While the schematic design for such busses may amount to simply wiring one pin to another, the PCB layout can be quite complex. There are three broad reasons for this complexity. The first is that the input setup and hold time requirements at the DRAM must be met. The second is that the setup and hold time requirements for the address/command signals at the DRAM must be met. And finally, the DRAM between the DQS and CLK needs to line up approximately at each DRAM.
In general, DDR buses are challenging. Changing voltages and currents can create voltages and currents in neighboring channels that result in unintended crosstalk. Conversely, parallel busses are more susceptible to crosstalk because most of the signals are single-ended.
Additionally, with signal integrity challenges such as Inter Symbol Interference (ISI) and crosstalk on the DDR bus, it can be difficult to know what to validate in the first place. For the DRAMs, validation requirements are spelled out in the JEDEC documentation. However, these documents aren’t always intuitive. On the controller side, the validation requirements are usually more straightforward, as it’s in the best interest of the controller vendor for designs to be completed quickly and with high quality. Nevertheless, it is still up to the designer to make sure that the document and requirements are well understood.
So, how can simulation and analysis speed up the design of a functioning DDR system to reduce PCB spins and shorten the time to release and market? This white paper entitled “PCB Engineer’s Guide to Successful DDR Bus Design” will help you tackle the critical signal integrity concerns encountered when designing, simulating, and analyzing DDR buses as well as help you understand and address the DDR bus design challenges that can be problematic, even intimidating, to designers.
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