The advent of high-speed serial links added many challenges to the process of designing PCBs. In some ways, it made things easier by eliminating the complicated length-matching required for parallel busses like DDR(1,2,3,4). But mostly, it added challenges. One of the most notable challenges is the inability to measure the bus in a lab. The most obvious reason for this is that due to the fast edge rates of these busses, measuring at the pin is essentially the middle of the bus, so you don’t get a clean “endpoint” waveform. Even if it were possible, you would still need to measure on the “other side” of the receiver equalization to see what the receiver is seeing. In order to deal with these measurement limitations, many SERDES specs advocate the use of test fixtures. These test fixtures typically have a standard connector on them to allow them to plug into a customer board, with some trace routing to SMA connectors to allow a high-bandwidth connection to an oscilloscope. The oscilloscope then mimics the receiver equalization to generate an eye diagram. This is where simulation presents an advantage, by allowing you to look anywhere in the circuit, including inside the receiver after the equalization. Another advantage of simulation is the ability to generate worst-case conditions directly, without having to wait the long periods of time it might take to capture them in the lab.
To hear more about simulation and measurement, check out my recent article in PCDandF magazine.