Process of via design and verification

 

Designers dealing with SERDES channels pay more and more attention to signal via effects. Many literatures and guidelines talk about the approaches to correctly configure vias so that via effects on signals can be minimized. Such methods require detailed analysis of single via or differential via pair. With the help of accurate 3D field solvers, vias can be designed to have controlled noise in channels by specifying stackup and padstack. One needs to know that such detailed analysis is for via structure itself, it does not consider any influence from other components on board. After the pre-studied structure is put on board with routed nets, placed components, and drilled holes, coupling occurs between vias and those components. Then, the previously understood behavior can be affected and extra noises may present. Therefore, the discontinuity effect from the particular via (or via pair) needs to be simulated again with its immediate neighbors, such as nets, other vias, etc..

We can see now that proper designs of vias on SERDES channel actually involve two parts: designing via configuration in pre-layout environment (design), and verifying via performance in post-route environment (verification). The first part explores design space at the early stage of a design, while the second part makes certain the pre-defined structure behaves as expected in the product. Designers need to perform 3D analyses at the beginning and end of a design, which the integration of 3D field solver in an SI tool is necessary. Read this article to get the details on the design and verification process with 3D field solver integration in SI environment.  

http://pcdandf.com/cms/component/content/article/171-current-issue/8975-integrated-3d-analysis

 

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/electronic-systems-design/2012/07/11/process-of-via-design-and-verification/