Put the Pieces in Place for SERDES Success
Interconnect loss modeling? Check.
Signal conditioning modeling? Check.
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain? Oooh…. that’s a tough one. Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis? Wow! Check.
3D via modeling? Check!
HyperLynx 8.2 is fully equipped to handle every SERDES problem you can throw at it. Really, any signal integrity problem you can throw at it. Power integrity too.
In general, SERDES designs are a lot easier to implement than parallel busses. You have a smaller number of problems to worry about, but the problems that are there are considerable. They are basically problems of fast edges and low margins. The fast edges require careful attention to detail in all aspects of the layout, and bring about the need to analyze pieces of the interconnect that could be ignored with slower edges, most notably vias. And the low margins necessitate a greater understanding of when the bus will actually fail. So in order to be successful in the analysis of these busses, care must be taken to include everything that is needed to understand the limits.
Read more about it in my recent article in New Electronics magazine: