Calibre Design Solutions at Samsung SAFE Forum: technology leadership through innovation, intelligence, and integration
Since 2018, Samsung Foundry has operated their foundry ecosystem program, called SAFE™ (Samsung Advanced Foundry Ecosystem), to ensure deep collaboration between partners and customers as they deliver competitive and robust system-on-chip (SoC) designs based upon Samsung’s process technologies.
A few weeks ago, Samsung Foundry, its ecosystem partners, and their joint customers came together at the 2021 Samsung SAFE Forum to talk about the latest advancements in technology, services, and tools that are helping Samsung and their customers deliver these resilient, market-ready SoC and IP designs. The theme of the forum was “Performance Platform 2.0: Innovation, Intelligence, Integration,” with focus on the design infrastructures required for multiple high-performance applications, and the technologies that ensure their success.
Siemens EDA participation in Samsung’s SAFE 2021 was led off by a keynote talk from A.J. Incorvaia, senior vice-president of the electronic board systems division at Siemens Digital Industries Software. In his speech, titled Enabling Intelligence, Innovation and Integration in Semiconductor Packaging, A.J. discussed the many ways in which Samsung Foundry and Siemens have collaborated to improve and expand EDA packaging tools, technologies, and semiconductor processes to support our mutual customers as they strive to deliver innovative “more than Moore” products to the market via 2.5/3D design approaches.
The Siemens Calibre Design Solutions group presented a variety of technical sessions to highlight the work we have done with Samsung and other ecosystems partners like Microsoft Azure, reinforcing the fact that customers come to Calibre first for help in addressing their verification issues.
Calibre Shifts-Left into place-and-route design flows
Swathi Rangarajan, Jeff Wilson
Swathi and Jeff explained how Samsung Foundry leverages the Calibre RealTime Digital DRC and fill flows, as well as Calibre YieldEnhancer and Calibre DesignEnhancer functionality, on their internal designs to improve their P&R design flows and productivity. They presented four flows demonstrating specific areas where Calibre products add faster overall turnaround time for designers working in P&R cockpits.
Calibre high performance compute for fast turn arounds
John Ferguson with Richard Paw and Giancarlo DiPasquale (Microsoft Azure)
John shared the results of the most recent joint collaboration between Siemens EDA, Microsoft Azure, and Samsung Foundry to develop best practices for ensuring the best runtimes and throughput for Calibre nmDRC by leveraging Microsoft Azure cloud scaling. The discussion also highlighted the other Calibre offerings that have already been validated to run on cloud, like the Calibre nmDRC Recon tool, so that a faster overall verification cycle time can be achieved on the cloud, not just large batch DRC runs.
Enabling accurate circuit simulation as silicon processes continue to evolve
Chris Clee
New process nodes enable improved price, performance, area (PPA), but they also require adaptation to new process techniques and dependencies, greater complexity, and new transistor structures. Predictable silicon simulation requires a parametric and parasitic extraction paradigm that accurately characterizes these new effects, to ensure simulation results are a true predictor of silicon performance. Chris presented the solution that Samsung Foundry and Siemens developed to ensure their joint customers’ designs could achieve ensure both fast and accurate parasitic extraction results when migrating to Samsung’s most advanced process nodes.
Siemens EDA 3.5D MDI Solution to improve PSI optimization, and validate implementation as well as verification of Si-interposer
Keith Felton, John Ferguson
In collaboration with Samsung Foundry, Siemens EDA developed, validated, and documented a “More than Moore” reference flow that starts with the creation of a 3.5D digital-twin model and then drives all aspects of downstream implementation, analysis, verification and signoff that works across all 2.5D and 3D IC approaches to spot potential issues and avoid building in constructs that will cause failures or require major re-design. Keith and John highlighted three key functionalities: Xpedition Package Designer enables early-stage signal integrity of HBM memory interface analysis of Si-interposer; HyperLynx supports SerDes channel analysis with TSV modeling and extraction; and Xpedition Substrate Integrator enables system-level netlist generation for Calibre 3DSTACK LVS to run final sign-off of heterogeneous 3.5D structures.
All technical presentations will be available for viewing through December 17th. If you were unable to attend the live event, but would like to hear the details of any of these presentations, you can still register this week at the SAFE Forum site.
