Enhance your User2User conference experience! Sign up for a training session the day after User2User Silicon Valley. Receive a free Siemens EDA ODT subscription. Keep on learning all year long.

User conferences are a great way to network and learn from your peers.  Like last year, we are excited to offer our users a chance to join in the day after User2User Silicon Valley and attend one or both of our live Technical Training Sessions on May 21, 2025.  Our industry experts in “Functional Verification” and “Design for Test” spaces will help you learn new technical topics to help increase your productivity with Siemens EDA tools and solutions.  Each training session, held in lecture format, will last for three hours. If you think 3 hours is not enough to train on these topics, you are right!!   Each participant will receive a free subscription for the full self-paced training course covered during these sessions. That will enable users to learn the entire topic and perform hands-on labs in our virtual cloud-based environment – no need to install and set up the software – normally, a $2500 value is provided only to registered User2User attendees who sign up for one or both training sessions before the conference.

Space is limited and filling up fast. Each training will be offered once at the Santa Clara Marriott. You can sign up for one or both training sessions during the U2U registration process by following this link. 

Meet our expert instructors and get ready for an exciting User2User.

Here is a look at the training sessions we are offering on May 21, 2025:

9 am – 12 pm:  Introduction to Software Design Pattern Concepts in SystemVerilog and UVM

This three-hour technical presentation will focus on software design patterns and their use in Universal Verification Methodology (UVM).

This technical training session’s intended audience consists of design and verification engineers familiar with SystemVerilog who have some exposure (though not required) to UVM.

• Review class-based object-oriented programming
  • Inheritance
  • Dynamic Polymorphism with Virtual Methods
  • Static Polymorphism with parametrized template classes
  • Interface classes
• Review Basic Software Design Patterns
  • Singleton, Factory, Proxy, Strategy/Policy

1 pm – 4 pm: Overview of the IEEE 1687 IJTAG standard and its use in Tessent

This IJTAG standard, released in 2014, has greatly impacted design-for-test. This session will cover the basics of the standard and how it is used extensively in the Tessent tools flows to improve design testability.

For this training session, design and test engineers familiar with basic DFT concepts should attend.

• Get an introduction to the IEEE 1687 standard and understand why it was created.
• Take a look at IJTAG’s two languages: ICL and PDL.
• Learn about the processes for ICL Extraction and PDL Retargeting.
• Understand how IJTAG is used in Tessent flows.
• Take home access to a self-paced full version of this training class, as well as the ability to perform hands-on labs. 

Register Now: We look forward to seeing you in these sessions on May 21 and the previous day, May 20, in the User2User exhibit hall to discuss any other training-related questions. You will also have a chance to take a certification exam of your interest and earn a digital badge that you may use to highlight your achievement on social media, email signatures, and elsewhere. Please visit the Training Session Overview page for more information about the training sessions and biographies of the presenters.