Enhance your User2User conference experience! Sign up for a training session the day before U2U Silicon Valley. Receive a free Siemens EDA ODT subscription. Keep on learning all year long.
User conferences are a great way to network and learn from your peers. This year, for the first time, we are excited to offer our users a chance to join in the day before U2U Silicon Valley and attend one or both of our live Technical Training Sessions scheduled on April 3, 2024. Our industry experts in “Functional Verification” and “Design for Test” will help you learn new technical tips to help increase your productivity with Siemens EDA tools and solutions. You will also have a chance to claim a digital badge certification. Each training session, held in lecture format, will last for three hours. If you think 3 hours is not enough to train on these topics, you are right!! Each participant will receive a free subscription for the full self-paced training course covered during these sessions. That will enable users to learn the entire topic and perform hands-on labs in our virtual cloud-based environment – no need to install and set up the software – normally a $2500 value is provided only to registered U2U attendees who sign up for one or both training sessions before U2U.
Do not miss the early bird registration, which ends on Friday, March 1. Space is limited and filling up fast. Each training will be offered twice, once each in the morning and afternoon of April 3, 2024, at Santa Clara Marriott. You can sign up for one or both training sessions during the U2U registration process by following this link.
Meet our expert instructors and get ready for an exciting U2U.
Here is a look at the training sessions we are offering:
UVM Functional Coverage
9:00 am-12:00 pm or 1:00 pm-4:00 pm
Who should attend: Design and verification engineers familiar with Questa, SystemVerilog, and UVM. They may have implemented parts of this flow but have not seen the big picture.
• Review of UVM testbench topology and transaction flow
• A Refresher on SystemVerilog functional coverage
• Discovering how to create a reusable UVM coverage collector
• Identifying common coverage collector issues
• Exploring functional coverage in the UVM register layer
Tessent Streaming Scan Network
9:00 am-12:00 pm or 1:00 pm-4:00 pm
Who should attend: Design and test engineers familiar with basic DFT concepts and compression ATPG with Tessent TestKompress.
• Learning about the need for and benefits of Tessent SSN
• Exploring the different SSN components and overall architecture
• Seeing how to implement SSN for a sample design
• Hearing about details for designs with duplicated cores
Register Now: We look forward to seeing you in these sessions and on the next day, April 4, in the U2U exhibit hall to discuss any other training-related questions. You will also have a chance to take a certification exam of your interest and earn a digital badge that you may use to highlight your achievement on social media, email signatures, and elsewhere. Please visit NEW! Technical Training (siemens.com) for more information about the training sessions and biographies of the presenters.
