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Nicolae Tusinschi
Product Manager Static and Formal Solutions

Nicolae Tusinschi is a product manager for static and formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental, Nicolae joined OneSpin, where he worked in QA, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics, leveraging coverage results in the verification process, formal verification of RISC-V cores.

Beyond simulation: Unlocking absolute certainty in hardware design with formal verification

Beyond simulation: Unlocking absolute certainty in hardware design with formal verification

February 16, 2026
Explore how formal verification is revolutionizing hardware design by offering not just confidence, but absolute certainty in design's correctness.
By Nicolae Tusinschi
< 1 MIN READ
osmosis 2024 – pushing the boundaries of formal verification

osmosis 2024 – pushing the boundaries of formal verification

December 11, 2024
Thank you for making osmosis 2024 a success! The annual osmosis 2024 event has once again proved to be a...
By Nicolae Tusinschi
< 1 MIN READ
Exploring essential concepts in Formal Verification

Exploring essential concepts in Formal Verification

September 18, 2024
What is a witness? is it the same as a counterexample? A witness is a sequence of inputs that demonstrates...
By Nicolae Tusinschi
< 1 MIN READ
Assertions and benefits of abstractions in Formal Verification

Assertions and benefits of abstractions in Formal Verification

September 11, 2024
How are assertions specified? Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These...
By Nicolae Tusinschi
< 1 MIN READ
Understanding Formal Verification

Understanding Formal Verification

September 5, 2024
What is formal verification? Formal verification is a method to ensure that a hardware design behaves as intended by using...
By Nicolae Tusinschi
< 1 MIN READ