No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

In formal verification, proving all of your properties is pretty much the main goal of the whole exercise – if…

How to Save a Ton of Time and Energy by Prioritizing Faults with Exhaustive Formal Analysis Before Launching Detailed Fault Verification

How to Save a Ton of Time and Energy by Prioritizing Faults with Exhaustive Formal Analysis Before Launching Detailed Fault Verification

[Preface: If you are going to be at ARM Techcon 2017 on Wednesday October 25, the methodology described in this…

DVCon China: Formal Technology Is Set for Growth in Asia

DVCon China: Formal Technology Is Set for Growth in Asia

At the recent DVCon in Shanghai, China, my colleague Jin Hou delivered the tutorial “Back to Basics: Doing Formal the…

How To Connect Your Testbench to Your Low Power UPF Models

How To Connect Your Testbench to Your Low Power UPF Models

Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL….

How Formal Techniques Can Keep Hackers from Leaving You in the Cold

How Formal Techniques Can Keep Hackers from Leaving You in the Cold

While internet connected vehicles remain a popular target for hackers, the new breed of “smart” devices have the potential to…

3 Things About UPF 3.0 You Need to Know Now

3 Things About UPF 3.0 You Need to Know Now

UPF 3.0 has been an official IEEE standard since January, but its most valuable capabilities have only become clear as…

How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC

How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC

It’s axiomatic that digital circuitry must initialize properly before it’s used. Once upon a time, verifying a design’s reset signaling…

5 Things I Learned at the 2016 SAE World Congress

5 Things I Learned at the 2016 SAE World Congress

A few weeks ago I had the honor of presenting a paper related to my prior Verification Horizons blog posts…