With a focus on design verification technologies at Siemens EDA, I help manage & develop EDA and IP standards and cultivate ecosystems around our solutions.
A great technical program awaits you for DVCon India 2016! The DVCon India Steering Committee and Technical Program Committee have…
Join us at the 53rd Design Automation Conference DAC is always a time of jam-packed activity with multiple events that…
First Debut of Working API at DVCon U.S. 2016 The Debug Data API is set to make its first public…
Join Us at DVCon As an annual conference, DVCon has set itself apart from others. With a high focus on…
Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in the functional verification of electronic…
Join us to review the first public review of the Debug Data API specification! At DAC 2015 we introduced Verification…
Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources. The tools…
Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2. But the moment…
If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…
