Chris Spear

Chris brings over forty years of EDA expertise to Siemens customers. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 12,000-foot mountain passes.

Starting Your UVM Simulation

Starting Your UVM Simulation

October 10, 2023
Introduction What happens when you start your simulation with a UVM test bench? Where should you put the uvm_config_db::set() calls...
By Chris Spear
< 1 MIN READ
A Hitchhiker’s Guide to DVCon US ’23

A Hitchhiker’s Guide to DVCon US ’23

June 27, 2023
Where can you improve your verification skills? In March 2023 I attended DVCon US, the Verification and Design Conference in...
By Chris Spear
< 1 MIN READ
Groups of Class Specializations in SystemVerilog

Groups of Class Specializations in SystemVerilog

April 25, 2023
Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a...
By Chris Spear
< 1 MIN READ
The UVM Factory Revealed, Part 2

The UVM Factory Revealed, Part 2

January 25, 2023
Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here...
By Chris Spear
< 1 MIN READ
UVM Factory Revealed, Part 1

UVM Factory Revealed, Part 1

January 20, 2023
Introduction When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming....
By Chris Spear
< 1 MIN READ
Does Your UVM Flavor Have Sprinkles?

Does Your UVM Flavor Have Sprinkles?

October 20, 2022
Introduction UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not...
By Chris Spear
< 1 MIN READ
Dig a Pool of Specialized SystemVerilog Classes

Dig a Pool of Specialized SystemVerilog Classes

October 17, 2022
Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if...
By Chris Spear
< 1 MIN READ
SystemVerilog: Implicit handles

SystemVerilog: Implicit handles

September 6, 2022
Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some...
By Chris Spear
< 1 MIN READ
SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

August 29, 2022
Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code....
By Chris Spear
< 1 MIN READ
SystemVerilog: What is a Virtual Interface?

SystemVerilog: What is a Virtual Interface?

August 21, 2022
When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why...
By Chris Spear
< 1 MIN READ
Getting Started with Questa Memory Verification IP

Getting Started with Questa Memory Verification IP

March 18, 2021
By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on a Chip is with design...
By Chris Spear
< 1 MIN READ
The UVM Config DB and Scope

The UVM Config DB and Scope

November 2, 2020
Introduction With any large software project, you need to share information and control across widely separated blocks. In the bad...
By Chris Spear
< 1 MIN READ
UVM Transaction Coding Style

UVM Transaction Coding Style

October 26, 2020
How to write a UVM transaction class? There has been a split in UVM – how to create a sequence...
By Chris Spear
< 1 MIN READ
Why are UVM transactions built with uvm_sequence_item?

Why are UVM transactions built with uvm_sequence_item?

September 28, 2020
What is a UVM transaction? A transaction in UVM is a class with properties for the signals, such as address...
By Chris Spear
< 1 MIN READ
What Does Importing a SystemVerilog Package Mean?

What Does Importing a SystemVerilog Package Mean?

July 15, 2020
In my last webinar I explained what happens when you import a package in SystemVerilog. There were still many questions,...
By Chris Spear
< 1 MIN READ
Get Your Bits Together

Get Your Bits Together

June 30, 2020
After my last webinar on SystemVerilog arrays, I received several questions on the differences between arrays and structures, plus how...
By Chris Spear
< 1 MIN READ
SystemVerilog Multidimensional Arrays

SystemVerilog Multidimensional Arrays

June 9, 2020
You asked and I listened Thank you everyone who registered and attended my webinar on SystemVerilog arrays. There were many...
By Chris Spear
< 1 MIN READ
Getting Organized with SystemVerilog Arrays

Getting Organized with SystemVerilog Arrays

May 28, 2020
SystemVerilog has many ways to store your data. Vectors, arrays, structures, classes, and probably several more ways that I don’t...
By Chris Spear
< 1 MIN READ
UVM Configuration DB Guidelines

UVM Configuration DB Guidelines

May 7, 2020
Introduction My previous blog posts were on static and parameterized classes to get you ready for the big game –...
By Chris Spear
< 1 MIN READ
SystemVerilog Static Methods

SystemVerilog Static Methods

April 29, 2020
Introduction In my last post, you learned how to create a class with a static property. This variable acts like...
By Chris Spear
< 1 MIN READ
SystemVerilog Classes with Static Properties

SystemVerilog Classes with Static Properties

April 21, 2020
Introduction One of the advantages of creating your testbenches with Object Oriented Programming, as opposed to traditional procedural programming, is...
By Chris Spear
< 1 MIN READ
SystemVerilog Parameterized Classes

SystemVerilog Parameterized Classes

April 16, 2020
SystemVerilog allows you to create modules and classes that are parameterized. This makes them more flexible, and able to work...
By Chris Spear
< 1 MIN READ
Tips for new UVM users

Tips for new UVM users

April 1, 2020
Or: What I forgot in class When I first learned UVM, there were many things that baffled me. What was...
By Chris Spear
< 1 MIN READ