Thought Leadership

Deploying HLS into a DO-254/ED-80 workflow

March 30, 2021 • 2 MIN READ
By Jake Wiltgen

To remain competitive in a challenging market, avionics companies continue to innovate across all aircraft-related systems, including flight management, communication, navigation, and in-flight entertainment. New features and capabilities demanded on board aircraft have a direct impact on the complexity of semiconductor design and verification. To meet these challenges, companies must adopt new design and verification methodologies making their engineers more efficient.

However, the adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. One tool which is showing increased interest and adoption in DO-254 workflows is High-Level Synthesis.

What is High-Level Synthesis (HLS)

High-Level Synthesis is an automated process which interprets an algorithmic description of design behavior (represented in SystemC or C++) and synthesizes that abstracted design model into digital hardware (Verilog/VHDL). Providing a C to gates translation allows engineers to rapidly create complex algorithms and makes the task of hardware design accessible to software engineers. Figure-1 below details a traditional HLS design flow.

Figure 1 – Generic HLS Design Workflow

Challenge using HLS in DO-254

Historically, the adoption of new technologies face resistance when deploying into DO-254 workflows. This resistance is present until technologies are properly vetted and confidence obtained. HLS is no different as we are considering a new level of design abstraction. The adoption of HLS is similar to the move to RTL design modeling, now a widely accepted representation for design entry.

Deploying HLS into a DO-254/ED-80 Workflow

To successfully deploy HLS technology into a DO-254 workflow, one must demonstrate tool confidence. Successful deployment requires describing the intended use of the tool as well as delivering the evidence and artifacts demonstrating correct behavior over the intended use model. This includes activities and work products in Planning, Requirements Capture, Conceptual Design, and Detailed Design.

Siemens EDA and Patmos Engineering teamed up to guide project teams on the deployment of HLS in a DO-254 flow and define how the unique feature set of Siemens EDA Catapult High-Level Synthesis helps project teams satisfy DO-254 objectives. The guidance can be found in the white paper titled “Deploying High-Level Synthesis in a DO-254/ED-80 Workflow” .

Jacob Wiltgen
Director, IC Verification Solutions

Jake Wiltgen is a Solutions Director at Siemens, responsible for divisional strategy in Automotive, Functional Safety, 3DIC, Rad-Hard, and High Performance Compute markets across the digital verification technologies portfolio. Moreover, Jake serves as the co-chair of the Front-End Design Track for the Digital Analog Design Conference (DAC) and is a primary representative for Siemens EDA in numerous automotive and functional safety standardization initiatives within Accellera and IEEE. He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Siemens, Jake held various design, verification, and leadership roles performing IC and SOC development at Xilinx, Paneve, Micron, and Broadcom.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2021/03/30/deploying-hls-into-a-do-254-ed-80-workflow/