Thought Leadership

Your lesson plan for DVCon Europe 2026

October 28, 2026 • 2 MIN READ
By Joe Hupcey III

In support of Verification Academy’s educational mission, Siemens is either directly sponsoring or contributing to the following tutorials and technical presentations at the upcoming DVCon Europe 2026 on Tuesday November 17 and Wednesday November 18.

These will address a wide range of D&V topics, from novice to expert level: whether it’s the latest on applying Agentic AI technology to accelerate verification closure, formal verification, high-level synthesis (HLS), HW-SW co-verification, and more.

And of course, please follow-up with our presenters and other domain experts at expo booth 21.

Tuesday, November 17

11:00 AM – 12:30 PM | Forum 4
Tutorial: Agentic AI for Chip Design
Darron May, Mark Carey

4:30 PM – 6:00pm | Forum 7
Tutorial: A Hybrid Formal and Simulation Verification Methodology for Accelerated Coverage Closure
Ahmed Selhi, et.al.

Wednesday, November 18

10:30 AM – 12:30 PM l Forum 7
Protocol, Interface & Mixed-Signal Verification I
A Reusable Verification Framework for Deep Learning Accelerators Using PyUVM and Cocotb
Amr Gamal, Essraa Moussoud, Mohamed Nafea

2:30 PM – 3:50 PM l Forum 5
Formal Verification, Coverage Methodology II
Toward Agentic Formal Verification: A Case study on Verification FPUs
Keerthi Devarajegowda, Moustafa Kishar, Sven Beyer, Joerg Grosse

2:30 PM – 3:50 PM | Forum 8
Safety, Security, DFT & Design Automation II
From Security-Hardened CPU to Safety Element out of Context Candidate: An FMEDA and Fault Simulation Case Study on Open Titan rv_core_ibex
Mahmoud Ali Hassan, Islam Ahmed, Mohamed Ayman, Abdulrahman Badawy, Eslam Mamdouh, Peter Azmy

How Robust Are Neural Accelerator Internals? A Pre-Silicon Deep Fault Injection Study of NVDLA
Eyad Gamal, Moustafa Nabil, Ahmed Makram, Mohamed Gamal

2:30pm – 3:50pm | Forum 8
AI/ML & Agentic Verification II
Breaking the Circularity of Trust: Mutation-Qualified Verification of LLM-Generated Predictor-Checkers
Krishan Gopal

4:30 PM – 5:50 PM | Forum 5
Formal Verification, Coverage & Verification Methodology III
Cross Coverage that Breaks the Hardware/Software Boundary
Russell Klein

Reference link: the complete DVCon Europe 2026 program grid.

Join us!

The Siemens EDA D&V Team

Joe Hupcey III

I am a product marketing and management professional, who brings a unique combination of hands-on engineering experience, an insightful understanding of what customers need in today’s ever-growing complex environment, and a proven ability to create winning messages that differentiate my company’s offerings from those of the competitors’. The context of this activity is the high-stakes race for more powerful chips and systems, whose complexity continues to double every 18 months even today.

What to read next:
This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2026/10/28/your-lesson-plan-for-dvcon-europe-2026/