The DVConUS 2022 issue of our Verification Horizons newsletter is now available. As always, we have a great slate of articles in this issue.
- NVMe-oF – Simple, Invisible Fabric to Cloud Storage: Learn some of the advantages of the new NVMe-OF (Non-Volatile Memory Express Over Fabrics) protocol for memory-intensive applications, allowing faster and more efficient connectivity between storage and servers while reducing CPU utilization on the host servers, and see how the NVMe-OF QVIP component can help you build a verification environment to handle these issues.
- Getting to Know Visualizer (Part 1): Introduction to our new Visualizer Debug Environment, which gives you a unified user interface to all our functional verification tools.
- Enabling Model-Based Design for DO-254 Certification Compliance (MathWorks): Discussing a Model-Based workflow driven by requirements that uses Simulink and Questa together to take you from concept through the implementation of a DO-254-compliant project.
- How do you “Qualify” Tools for DO-254 Programs? (Patmos Engineering Services): A walk through the complicated process to qualify a tool to be used in a DO-254 project. As you’ll see, the advantage of having DO-254 specialists like Patmos as partners is that we’ve already qualified our tools, so at any step of a DO-254 project, you can be confident that your Siemens EDA tool is the right tool for the job.
- Reflections on Users’ Experiences With SVA (Part 1): Noted SystemVerilog Assertions expert Ben Cohen share his thoughts on some of the “gotchas” that he’s seen over the years. Part One covers Ben’s recommendations for expressing requirements for assertions and hits some critical SVA concepts and terminology.
- A Faster Approach to Co-simulation using Questa and VPI (Bitec): Introduces a unique VPI library that works with their VIP to run software in a simulation without the overhead of the CPU model.
- UVVM – The World’s Number One VHDL Verification Methodology for Faster and Better FPGA And ASIC Verification (EmLogic): Introduction to the Universal VHDL Verification Methodology, bringing the SystemVerilog UVM concepts of structured modular, reusable verification components to the VHDL community to make VHDL verification more effective and efficient.
In addition to these great articles, you can also see how I’m using simulation to improve my golf game. Please check out this latest issue of Verification Horizons. For more information about Siemens EDA content at DVConUS, please see here.