Now that we’re well into autumn, it’s time for our November issue of Verification Horizons. As always, we have a great assortment of technical articles for your enjoyment and edification, from some of my Mentor colleagues as well as from some of our partners:
- Quantifying FPGA Verification Effectiveness: A summary of Harry Foster’s biennial industry survey, focusing on how well we’re doing in verifying FPGAs. For more details about Harry’s study, see here.
- Arasan MIPI® CSI-2-RX IP Verification Using Questa® VIPs: A case study of how Arasan used Questa® Verification IP (QVIP) to verify their MIPI Camera Serial Interface peripheral device.
- Memory Softmodels – The Foundation Of Validation Accuracy: An examination of how Memory Softmodels provide a consistent configurable model that can be used in emulation and FPGA prototyping to validate “real” software before the design is complete.
- Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver [Silicon Interfaces]: A case study on how they applied coverage automation in Questa inFact to automate testcase generation and meet their coverage goals.
- A Unified Approach to Verify Complex FSM [eInfochips]: An exploration of their innovative UVM-based approach to verifying complex finite state machines by randomly generating custom scenarios to traverse all available paths.
- RISC-V Design Verification Strategy [Tessolve and InCore]: An exploration of multiple techniques to ensure your RISC-V core accurately implements your instruction set and functions correctly in your application.
In addition, you’ll learn about how an “old dog” like me learned a new trick in lawn maintenance by applying some new technology. Check it out!