Thought Leadership

Great Upcoming Web Events on the Horizon

By Tom Fitzpatrick

We’ve had some great online web seminars these past few weeks. Please consider viewing the on-demand recordings:

SystemVerilog & UVM:

  • UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know
  • Taking SystemVerilog Arrays to the Next Dimension
  • Get Your Bits Together: SystemVerilog Structures and Packages
  • Stimulating Simulating: UVM Transactions
  • Stimulating Simulating 2: UVM Sequences

Formal Verification – Should I Kill My Formal Run:

  • Part 1: What You Can Do While the Formal Run is In-Progress
  • Part 2: What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success

Functional Safety – ISO 26262:

And for those of you in the PacRim area, we’ve got some, too

I hope you enjoy these great web presentations.

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This article first appeared on the Siemens Digital Industries Software blog at