Thought Leadership

Portable Stimulus in Verification Horizons

By Tom Fitzpatrick

Welcome back from Summer! Now that we’re all re-focusing on work after vacations, I wanted to remind everyone about a couple of great Portable Test & Stimulus articles in our most-recent issue of Verification Horizons to get you back into the swing of things.

In “Smoothing the Path to Software-Driven Verification with Portable Stimulus,” our resident Portable Stimulus guru, Matthew Ballance, takes you through a step-wise approach to verifying the interactions between your embedded processor(s) and the IP blocks in the rest of your design. Specifying a declarative model of the interactions using Portable Stimulus lets you generate a robust set of regressions from a single source. The abstraction built into Portable Stimulus lets a tool like Questa inFact create both UVM and C-based implementations of the same tests as your verification environment moves from the block to the system level.

Then, in “Portable Stimulus Modeling in a High-Level Synthesis User’s Verification Flow,” two key members of our High-Level Synthesis team show you how this “one-model-to-multiple-implementations” idea of Portable Stimulus can be extended to create constrained-random, coverage-driven tests for your high-level SystemC/C++ model earlier in the process. Not only does this make your initial high-level tests more exhaustive and productive, it also lets you reuse these tests as you refine your design to RTL and then through the rest of your verification flow.

There are, of course, several more great articles in this issue, so I encourage you to look at those, too. But I especially wanted to call your attention to these two articles since they do such a good job of explaining the breadth and context of the applications of Portable Test & Stimulus throughout the verification flow. Enjoy!

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This article first appeared on the Siemens Digital Industries Software blog at