New Verification Horizons Issue Available

Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view the articles or download the issue here. In addition to a little paternal bragging in the Introduction, I wanted to call your attention in particular to a few of the articles written by some Mentor colleagues:

• Software-Driven Testing of AXI Bus in a Dual Core ARM System by Mark Olen, Mentor Graphics
  In this article, Mark presents an architecture for verifying the functionality and performance of a complex AXI bus fabric using a combination of SystemVerilog and C software-driven test techniques, where the operation of the C code is automatically coordinated with additional UVM stimulus to ensure that you’re hitting corner cases of your software as well as your hardware.
• Caching in on Analysis by Mark Peryer, Mentor Graphics
  Our “other Mark” explains how to verify complex interconnect subsystems in Questa through testbench and instrumentation generation, as well as automated stimulus to target interconnect functionality and cache coherency.
• DDR SDRAM Bus Monitoring using Mentor Verification IP by Nikhil Jain, Mentor Graphics
  Here, Nikhil explains how Mentor’s DDR VIP can be used as a bus monitor, taking advantage of builtin coverage and assertions, to ensure proper protocol behavior.
• Life Isn’t Fair, So Use Formal by Roger Sabbagh, Mentor Graphics
  Roger will show you how to use Questa CoverCheck to help you reach (or usually eliminate) that last 10% of code coverage that always seems to take so long.

I had to write my introduction before the Red Sox actually made it to the World Series, but I just have to say that

1. I picked the Sox to beat the Tigers in 6 games in the ALCS (including calling Big Papi’s grand slam in game two – ask my son), and
2. I picked the Sox to beat the Cardinals in 6 games to win the World Series.

Just wanted you all to know that.

-Tom