DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation

I’d like to encourage you to attend the technical panel titled Bridging Pre-Silicon Verification and Post-Silicon Validation at this year’s  DAC.  The panel will be held on Tuesday, June 15, 2010 between 2:00 PM—4:00 PM.

Why do I think this is an important topic?  At 65nm, we witnessed the post-silicon validation effort often consuming more than 50% of an SoC’s overall design effort, as measured in cost, and the problem grows as the industry continues to move to even smaller geometries. Unlike pre-silicon verification, which has historically (and conveniently) partitioned the verification effort into separate concerns (such as, electrical, functional, performance, and software), identifying failures in post-silicon requires skills spanning multiple validation disciplines. Furthermore, the process of post-silicon validation is hindered by both poor observability and poor controllability. To address today’s escalating validation effort requires establishing a stronger link between the pre-silicon verification and post-silicon validation processes. Certainly assertions are one technique that can bridge pre- and post-silicon by providing improved observability on critical functionality. However, the improvements obtained by silicon assertions are only as effective as the quality of their pre-silicon form. Realistically, only a small set of critical assertions could be shared between the pre- and post-silicon processes. What is needed is a means to instrument into the silicon observability in a reconfigurable fashion, thus allowing the post-silicon validation engineer to shift focus on specific areas of concern. Concerning test generation, pre-silicon test provides insufficient coverage to stress the post-silicon design. Hence, what is needed is a means to capture post-silicon test associated with a failure in an abstract form that can be demonstrated on a pre-silicon model. Finally, concerning triage and error isolation, both the pre-silicon verification and post-silicon validation processes could benefit from automatic techniques that identify a set of candidate causes behind the detected failure.

For more information about the upcoming panel, visit: http://www2.dac.com/panels.aspx?event=30&topic=11