How AI is accelerating semiconductor testing
Microchips are some of the most complex devices on the planet and the design process that generates them is no less advanced, as first millions and now billions of individual elements are placed to deliver the desired functionality. However, an oft overlooked element of the semiconductor design process is the need for testing, a process that, due to the size and complexity of modern chips, must start well before the first physical chip is ever produced.
In a recent podcast, Ron Press, Senior Director of Technology Enablement at Siemens Digital Industries, delved into what it takes to design chips with testing in mind, the unique challenges faced in this process, and how that lead to the development of tools like Tessent. Beyond that, he also explores how AI is becoming a powerful tool for testing complex devices, and what that will mean for the future.
Check out the full episode here, or read the transcript here.
Understanding DFT
Making sure every chip that comes out of a foundry is 100% functional is crucially important, especially since these chips could end up in medical devices or cars or airplanes where any loss of function could have fatal results, Ron explains. Beyond simply catching failed chips, it is equally important to be able to determine the root cause of failure and, if possible, reduce its impact or eliminate it entirely. In order to achieve this, however, more than simply brute force testing every function on every chip is required – a process that would be physically impossible due to the shear amount of time it would take. Instead, chips must be designed from the very beginning with testing in mind, a process called design for test or DFT.
By employing DFT, it’s possible to optimize a chip design so that it can be tested quickly and efficiently using predefined test patterns. This not only means the testing process can be completed quickly for every chip, it also makes it easier to identify the root causes of any failures that do occur as well as provide a potential data source to train machine learning models on.
While DFT has many benefits, it’s not something that can be considered free from a design perspective either. Embedding test circuits into a chip design costs valuable area that could’ve been used for more processing power, or memory, or countless other things. Simply not testing chips isn’t an option either though, so when it comes to DFT, there’s always a fine line to walk include the absolute minimum of required testing structures that are still capable of fully validating a completed chips functionality, and this type of complex optimization is perfect for applying AI.
AI supports advancement
Ron explains there are two main areas that tools like Tessent leverage AI in, which are hierarchical DFT and what he calls analytical AI embedded in their Streaming Scan Network software, or SSN. Hierarchical DFT emerged from the fact that designs continued to grow bigger and bigger over time, which means that instead of optimizing a test pattern for a design as a whole it was instead done on a core-by-core basis and the results were aggregated to develop test patterns and optimizations for the final design.
Ron goes on to explain that, even when AI is applied to hierarchical DFT, to help do things like optimize bandwidth or improve embedded compression, the best result they could achieve was around 20 to 30% smaller pattern sizes. While this is by no means an insignificant improvement, it wouldn’t be enough to keep pace with the ever-increasing size of chip designs so instead, he and his team approached the problem from a completely different angle, which resulted in the creation of their analytical AI.
The SSN packetizes the testing data before its used to test the chip, rather than directly piping it to each core being tested. This means they can optimize the data delivery directly for the chip as a whole, reducing the amount of I/O test pins required, the amount of test circuitry within the chip and allowing all cores of a chip to be tested at the same time, within the same amount of time. The creation of this packetized test data can be heavily optimized as well, which is exactly where analytical AI comes into play, allowing them to remove the variables when it comes to DFT, designers can optimize their cores, make their test patterns then the AI within the SSN software handles the rest, devising an optimized, packetized test data suite without the need for manual heavy lifting.
Testing might not be a glamours job but it is vitally important both within the chip design industry and the manufacturing industry at large. With rigid standards to uphold, a huge number of variables to optimize for and vast quantities of data to work with, testing and verification is primed to receive a huge boost from AI, allowing for greater optimizations and efficiency then traditional methods alone could bring. As semiconductor designs grow ever more complex, the need to embrace cutting-edge technology to keep pace will be a must, with AI as one such technology that will be key in developing, and testing, the chips of tomorrow.
Siemens Digital Industries Software helps organizations of all sizes digitally transform using software, hardware and services from the Siemens Xcelerator business platform. Siemens’ software and the comprehensive digital twin enable companies to optimize their design, engineering and manufacturing processes to turn today’s ideas into the sustainable products of the future. From chips to entire systems, from product to process, across all industries. Siemens Digital Industries Software – Accelerating transformation.
